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/freebsd-13.1/sys/contrib/device-tree/Bindings/arm/cpu-enable-method/
H A Dal,alpine-smp6 enabling secondary CPUs. To apply to all CPUs, a single
12 Compatible CPUs: "arm,cortex-a15"
33 system fabric, like powering CPUs off.
H A Dmarvell,berlin-smp6 CPUs. To apply to all CPUs, a single "marvell,berlin-smp" enable method should
11 Compatible CPUs: "marvell,pj4b" and "arm,cortex-a9"
H A Dnuvoton,npcm750-smp5 To apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be
10 Compatible CPUs: "arm,cortex-a9"
/freebsd-13.1/sys/contrib/device-tree/Bindings/mips/brcm/
H A Dbrcm,bmips.txt1 * Broadcom MIPS (BMIPS) CPUs
7 - mips-hpt-frequency: This is common to all CPUs in the system so it lives
/freebsd-13.1/sys/contrib/device-tree/Bindings/arm/
H A Dpmu.yaml55 # Don't know how many CPUs, so no constraints to specify
66 nodes corresponding to the set of CPUs which have
90 not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux
H A Dcpu-capacity.txt2 ARM CPUs capacity bindings
18 CPU capacity is a number that provides the scheduler information about CPUs
20 (e.g., ARM big.LITTLE systems) or maximum frequency at which CPUs can run
23 capture a first-order approximation of the relative performance of CPUs.
237 [1] ARM Linux Kernel documentation - CPUs bindings
H A Dcci.txt21 root node (ie from CPUs perspective as per DT standard).
127 (inclusive of CPUs and their cpu nodes).
223 CCI slave interface @0x000000002c094000 is connected to CPUs {CPU0, CPU1};
224 CCI slave interface @0x000000002c095000 is connected to CPUs {CPU2, CPU3};
H A Dspe-pmu.txt12 SPE is only supported on a subset of the CPUs, please consult
H A Darm,realview.yaml14 11, Cortex A-8 and Cortex A-9 CPUs. This included new features compared to
15 the earlier CPUs such as TrustZone and multicore (MPCore).
/freebsd-13.1/share/examples/perfmon/
H A DREADME2 counters on Pentium and Pentium Pro CPUs. See perfmon(4) for a
15 The following options are not implemented on Pentium CPUs:
/freebsd-13.1/sys/contrib/device-tree/Bindings/mips/ingenic/
H A Dingenic,cpu.yaml7 title: Bindings for Ingenic XBurst family CPUs
13 Ingenic XBurst family CPUs shall have the following properties.
/freebsd-13.1/sys/contrib/device-tree/Bindings/clock/
H A Dqcom,msm8996-apcc.yaml7 title: Qualcomm clock controller for MSM8996 CPUs
13 Qualcomm CPU clock controller for MSM8996 CPUs, clock 0 is for Power cluster
H A Dclps711x-clock.txt1 * Clock bindings for the Cirrus Logic CLPS711X CPUs
/freebsd-13.1/contrib/llvm-project/compiler-rt/lib/scudo/standalone/
H A Dlinux.cpp138 cpu_set_t CPUs; in getNumberOfCPUs() local
141 if (sched_getaffinity(0, sizeof(cpu_set_t), &CPUs) != 0) in getNumberOfCPUs()
143 return static_cast<u32>(CPU_COUNT(&CPUs)); in getNumberOfCPUs()
/freebsd-13.1/sys/contrib/device-tree/Bindings/powerpc/fsl/
H A Dcpus.txt5 Power Architecture CPUs in Freescale SOCs are represented in device trees as
18 Power CPUs. The EREF defines some architecture categories not defined
/freebsd-13.1/contrib/googletest/googlemock/docs/
H A DKnownIssues.md9 ## Tests failing on machines using Power PC CPUs (e.g. some Macs) ##
11 `gmock_output_test` and `gmock-printers_test` are known to fail with Power PC CPUs. This is due to…
/freebsd-13.1/sys/i386/conf/
H A DNOTES47 # HTT CPUs should only be used if they are enabled in the BIOS. For
48 # the ACPI case, ACPI only correctly tells us about any HTT CPUs if
49 # they are enabled. However, most HTT systems do not list HTT CPUs
50 # in the MP Table if they are enabled, thus we guess at the HTT CPUs
52 # these CPUs if HTT is disabled. Thus, HTT guessing is only enabled
64 options MPTABLE_FORCE_HTT # Enable HTT CPUs with the MP Table
108 # of Cyrix 6x86 and 6x86MX CPUs by setting the NO_LOCK bit of CCR1.
148 # Pro BIOSs do not enable L2 cache of Mendocino Celeron CPUs.
160 # K5/K6/K6-2 CPUs.
826 # coretemp: on-die sensor on Intel Core and newer CPUs
[all …]
/freebsd-13.1/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Darm,gic-v3.yaml60 The 4th cell is a phandle to a node describing a set of CPUs this
165 used to route Message Signalled Interrupts (MSI) to the CPUs.
239 <0x2d000000 0x800000>, // GICR 1: CPUs 0-31
240 <0x2e000000 0x800000>, // GICR 2: CPUs 32-63
/freebsd-13.1/sys/contrib/device-tree/Bindings/timer/
H A Dsnps,archs-gfrc.txt1 Synopsys ARC Free Running 64-bit Global Timer for ARC HS CPUs
H A Dsnps,archs-rtc.txt1 Synopsys ARC Free Running 64-bit Local Timer for ARC HS CPUs
H A Dsnps,arc-timer.txt2 - Found on all ARC CPUs (ARC700/ARCHS)
/freebsd-13.1/sys/contrib/device-tree/Bindings/cpu/
H A Dcpu-topology.txt9 In a SMP system, the hierarchy of CPUs is defined through three entities that
10 are used to describe the layout of physical CPUs in the system:
20 For instance in a system where CPUs support SMT, "cpu" nodes represent all
33 correspond to physical CPUs and are to be mapped to the hierarchy levels.
48 Usage: Optional - On SMP systems provide CPUs topology to the OS.
154 If a core node is not a leaf node (CPUs supporting SMT) a core node's
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86SchedPredicates.td65 // on recent Intel CPUs.
77 // on recent Intel CPUs.
/freebsd-13.1/sys/contrib/device-tree/Bindings/cpufreq/
H A Dcpufreq-spear.txt6 which share clock across all CPUs.
/freebsd-13.1/lib/libpmc/pmu-events/
H A DREADME3 CPUs by their symbolic names rather than raw event codes (see example below).
44 - Set of 'PMU events tables' for all known CPUs in the architecture,
79 1. Several CPUs can support same set of events and hence use a common

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