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Searched refs:CONCAT_VECTORS (Results 1 – 24 of 24) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp120 setOperationAction(ISD::CONCAT_VECTORS, T, Custom); in initializeHVXLowering()
154 setOperationAction(ISD::CONCAT_VECTORS, T, Custom); in initializeHVXLowering()
224 setOperationAction(ISD::CONCAT_VECTORS, BoolV, Custom); in initializeHVXLowering()
366 return DAG.getNode(ISD::CONCAT_VECTORS, dl, typeJoin(ty(Ops)), in opJoin()
1051 SDValue InLo = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {SubV, V1}); in insertHvxSubvectorReg()
1244 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, V0, V1); in LowerHvxBuildVector()
1319 SDValue V0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfTy, in LowerHvxConcatVectors()
1321 SDValue V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfTy, in LowerHvxConcatVectors()
1798 SDValue S = DAG.getNode(ISD::CONCAT_VECTORS, dl, ResTy, L, H); in SplitHvxPairOp()
1831 { DAG.getNode(ISD::CONCAT_VECTORS, dl, MemTy, Load0, Load1), in SplitHvxMemOp()
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H A DHexagonISelLowering.cpp1652 ISD::CONCAT_VECTORS, ISD::VECTOR_SHUFFLE, in HexagonTargetLowering()
1702 setOperationAction(ISD::CONCAT_VECTORS, NativeVT, Custom); in HexagonTargetLowering()
2756 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResTy, Concats); in appendUndef()
3175 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); in LowerOperation()
H A DHexagonISelDAGToDAGHVX.cpp1708 LV = DAG.getNode(ISD::CONCAT_VECTORS, dl, ResTy, {L0, L1}); in scalarizeShuffle()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp623 case ISD::CONCAT_VECTORS: in ScalarizeVectorOperand()
1249 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps); in SplitVecRes_CONCAT_VECTORS()
1252 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps); in SplitVecRes_CONCAT_VECTORS()
1561 ISD::CONCAT_VECTORS, dl, OtherVT, in SplitVecRes_OverflowOp()
2362 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi); in SplitVecOp_UnaryOp()
2936 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); in SplitVecOp_FP_ROUND()
2959 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi); in SplitVecOp_FP_TO_XINT_SAT()
3275 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, in CollectOpsToWiden()
4159 else if (N.getOpcode() == ISD::CONCAT_VECTORS) { in isSETCCorConvertedSETCC()
5380 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, in GenWidenVectorLoads()
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H A DDAGCombiner.cpp9663 assert(LHS.getOpcode() == ISD::CONCAT_VECTORS && in ConvertSelectToConcatVector()
9664 RHS.getOpcode() == ISD::CONCAT_VECTORS && in ConvertSelectToConcatVector()
9704 ISD::CONCAT_VECTORS, DL, VT, in ConvertSelectToConcatVector()
10161 if (N1.getOpcode() == ISD::CONCAT_VECTORS && in visitVSELECT()
10162 N2.getOpcode() == ISD::CONCAT_VECTORS && in visitVSELECT()
18398 if (ArgVal.getOpcode() == ISD::CONCAT_VECTORS) { in combineInsertEltToShuffle()
20170 if (IndexC && V.getOpcode() == ISD::CONCAT_VECTORS && in getSubVectorSrc()
20480 if (V.getOpcode() == ISD::CONCAT_VECTORS) { in visitEXTRACT_SUBVECTOR()
21263 if (N0.getOpcode() == ISD::CONCAT_VECTORS && in visitVECTOR_SHUFFLE()
21266 (N1.getOpcode() == ISD::CONCAT_VECTORS && in visitVECTOR_SHUFFLE()
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H A DSelectionDAGDumper.cpp288 case ISD::CONCAT_VECTORS: return "concat_vectors"; in getOperationName()
H A DSelectionDAG.cpp2852 case ISD::CONCAT_VECTORS: { in computeKnownBits()
4102 case ISD::CONCAT_VECTORS: { in ComputeNumSignBits()
4850 case ISD::CONCAT_VECTORS: in getNode()
5206 if (Opcode >= ISD::BUILTIN_OP_END || Opcode == ISD::CONCAT_VECTORS) in FoldConstantArithmetic()
5582 case ISD::CONCAT_VECTORS: { in getNode()
5818 N1.getOpcode() == ISD::CONCAT_VECTORS && N1.getNumOperands() > 0) { in getNode()
5931 if (N1.getOpcode() == ISD::CONCAT_VECTORS && N1.getNumOperands() > 0 && in getNode()
6069 case ISD::CONCAT_VECTORS: { in getNode()
7960 case ISD::CONCAT_VECTORS: in getNode()
H A DLegalizeDAG.cpp1434 Node->getOpcode() == ISD::CONCAT_VECTORS) && in ExpandVectorBuildThroughStack()
2974 case ISD::CONCAT_VECTORS: in ExpandNode()
4777 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewOps); in PromoteNode()
4899 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewElts); in PromoteNode()
H A DLegalizeIntegerTypes.cpp117 case ISD::CONCAT_VECTORS: in PromoteIntegerResult()
1259 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2); in PromoteIntRes_TRUNCATE()
1495 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break; in PromoteIntegerOperand()
H A DSelectionDAGBuilder.cpp390 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS in getCopyFromPartsVector()
3618 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps)); in visitShuffleVector()
3636 Src1 = DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps1); in visitShuffleVector()
3637 Src2 = DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps2); in visitShuffleVector()
5485 case ISD::CONCAT_VECTORS: in getUnderlyingArgRegs()
H A DTargetLowering.cpp1100 case ISD::CONCAT_VECTORS: { in SimplifyDemandedBits()
2567 case ISD::CONCAT_VECTORS: { in SimplifyDemandedVectorElts()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h519 CONCAT_VECTORS, enumerator
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp353 setOperationAction(ISD::CONCAT_VECTORS, MVT::v3i32, Custom); in AMDGPUTargetLowering()
354 setOperationAction(ISD::CONCAT_VECTORS, MVT::v3f32, Custom); in AMDGPUTargetLowering()
355 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); in AMDGPUTargetLowering()
356 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom); in AMDGPUTargetLowering()
357 setOperationAction(ISD::CONCAT_VECTORS, MVT::v5i32, Custom); in AMDGPUTargetLowering()
358 setOperationAction(ISD::CONCAT_VECTORS, MVT::v5f32, Custom); in AMDGPUTargetLowering()
359 setOperationAction(ISD::CONCAT_VECTORS, MVT::v6i32, Custom); in AMDGPUTargetLowering()
360 setOperationAction(ISD::CONCAT_VECTORS, MVT::v6f32, Custom); in AMDGPUTargetLowering()
361 setOperationAction(ISD::CONCAT_VECTORS, MVT::v7i32, Custom); in AMDGPUTargetLowering()
362 setOperationAction(ISD::CONCAT_VECTORS, MVT::v7f32, Custom); in AMDGPUTargetLowering()
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H A DSIISelLowering.cpp286 case ISD::CONCAT_VECTORS: in SITargetLowering()
624 case ISD::CONCAT_VECTORS: in SITargetLowering()
4490 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi); in splitUnaryVectorOp()
4514 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi); in splitBinaryVectorOp()
4538 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi); in splitTernaryVectorOp()
5630 return DAG.getNode(ISD::CONCAT_VECTORS, SL, ResultVT, Pieces); in lowerVECTOR_SHUFFLE()
6439 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Loads); in lowerSBuffer()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp2012 setTargetDAGCombine(ISD::CONCAT_VECTORS); in X86TargetLowering()
5997 if (N->getOpcode() == ISD::CONCAT_VECTORS) { in collectConcatOps()
6066 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, in splitVectorIntUnary()
8077 if (Opcode == ISD::CONCAT_VECTORS) { in getShuffleScalarElt()
10136 ISD::CONCAT_VECTORS, DL, VT, in createVariablePermute()
13705 case ISD::CONCAT_VECTORS: { in lowerShuffleAsBroadcast()
38475 if (N0.getOpcode() != ISD::CONCAT_VECTORS || in combineShuffleOfConcatUndef()
44798 if (Src.getOpcode() != ISD::CONCAT_VECTORS) in combineScalarAndWithMaskSetcc()
45282 ISD::CONCAT_VECTORS, dl, VT, in combineOr()
45291 ISD::CONCAT_VECTORS, dl, VT, in combineOr()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp175 setTargetDAGCombine(ISD::CONCAT_VECTORS); in WebAssemblyTargetLowering()
2370 if (N->getOpcode() == ISD::CONCAT_VECTORS) { in performVectorTruncZeroCombine()
2481 case ISD::CONCAT_VECTORS: in PerformDAGCombine()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp907 setTargetDAGCombine(ISD::CONCAT_VECTORS); in AArch64TargetLowering()
1210 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in AArch64TargetLowering()
1261 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in AArch64TargetLowering()
1299 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in AArch64TargetLowering()
1436 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal); in addTypeForNEON()
1524 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in addTypeForFixedLengthSVE()
4819 case ISD::CONCAT_VECTORS: in LowerOperation()
9101 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1); in tryFormConcatFromShuffle()
9325 } else if (V.getOpcode() == ISD::CONCAT_VECTORS) { in constructDup()
16638 case ISD::CONCAT_VECTORS: in PerformDAGCombine()
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H A DAArch64InstrFormats.td9259 // intrinsic, represented by CONCAT_VECTORS.
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp184 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal); in addTypeForNEON()
433 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in addMVEVectorTypes()
7864 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lower, Upper); in LowerBUILD_VECTOR()
8002 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
9044 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ToVT, Ext, Ext1); in LowerVectorExtend()
9433 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); in LowerSDIV()
9470 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); in LowerUDIV()
14931 if (Op0.getOpcode() != ISD::CONCAT_VECTORS || in PerformVECTOR_SHUFFLECombine()
14932 Op1.getOpcode() != ISD::CONCAT_VECTORS || in PerformVECTOR_SHUFFLECombine()
14948 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, in PerformVECTOR_SHUFFLECombine()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp459 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in RISCVTargetLowering()
554 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in RISCVTargetLowering()
621 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in RISCVTargetLowering()
678 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); in RISCVTargetLowering()
1848 if (V.getOpcode() == ISD::CONCAT_VECTORS) { in lowerVECTOR_SHUFFLE()
2515 case ISD::CONCAT_VECTORS: { in LowerOperation()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp763 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand); in initActions()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td680 def concat_vectors : SDNode<"ISD::CONCAT_VECTORS",
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp2171 case ISD::CONCAT_VECTORS: in LowerOperation()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp8370 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WideVT, Ops); in widenVec()