| /freebsd-13.1/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | LoopCacheAnalysis.cpp | 149 unsigned CLS, in hasSpacialReuse() argument
191 bool InSameCacheLine = (Diff->getValue()->getSExtValue() < CLS); in hasSpacialReuse()
263 unsigned CLS) const { in computeRefCost()
289 if (isConsecutive(L, CLS)) { in computeRefCost()
293 const SCEV *CacheLineSize = SE.getConstant(Stride->getType(), CLS); in computeRefCost()
405 bool IndexedReference::isConsecutive(const Loop &L, unsigned CLS) const { in isConsecutive()
420 const SCEV *CacheLineSize = SE.getConstant(Stride->getType(), CLS); in isConsecutive()
541 unsigned CLS = TTI.getCacheLineSize(); in populateReferenceGroups() local
578 R->hasSpacialReuse(Representative, CLS, AA); in populateReferenceGroups()
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Analysis/ |
| H A D | LoopCacheAnalysis.h | 73 Optional<bool> hasSpacialReuse(const IndexedReference &Other, unsigned CLS,
93 CacheCostTy computeRefCost(const Loop &L, unsigned CLS) const;
106 bool isConsecutive(const Loop &L, unsigned CLS) const;
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZPatterns.td | 19 // in which the first operand has class CLS and which the second operand
56 // Record that INSN performs insertion TYPE into a register of class CLS.
148 // registers in CLS against zero. The instruction has separate R1 and R2
157 // on registers of class CLS.
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| /freebsd-13.1/share/syscons/fonts/ |
| H A D | iso08-8x14.fnt | 35 M`````````#MF9F8^!F8\````<#`P-CLS,S-S```````,#``<#`P,#!X`````
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| H A D | iso15-8x14.fnt | 35 M`````````#MF9F8^!F8\````<#`P-CLS,S-S```````,#``<#`P,#!X`````
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| H A D | iso-8x14.fnt | 35 M`````````#MF9F8^!F8\````<#`P-CLS,S-S```````,#``<#`P,#!X`````
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedTSV110.td | 406 def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "^(CLS|CLZ|RBIT|REV(16|32)?)(W|X)r$")>;
644 def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^(CLS|CLZ|CNT)v")>;
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| H A D | AArch64SchedCyclone.td | 151 // CLS,CLZ,RBIT,REV,REV16,REV32
501 // CLS,CLZ,CNT,RBIT,REV16,REV32,REV64,XTN
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| H A D | AArch64SchedFalkorDetails.td | 922 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^(CLS|CLZ|CNT|RBIT)(v2i32|v4i16|v8i8)$")>;
944 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(CLS|CLZ|CNT|RBIT)(v4i32|v8i16|v16i8)$")>;
1207 def : InstRW<[FalkorWr_1XYZ_2cyc], (instregex "^(CLS|CLZ|RBIT|REV|REV16|REV32)(W|X)r$")>;
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| H A D | AArch64SchedKryoDetails.td | 495 (instregex "(CLS|CLZ)(W|X)r")>;
501 (instregex "(CLS|CLZ|CNT)(v4i32|v8i16|v16i8)")>;
507 (instregex "(CLS|CLZ|CNT)(v2i32|v4i16|v8i8)")>;
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| H A D | AArch64SchedThunderX2T99.td | 558 def : InstRW<[THX2T99Write_3Cyc_I1], (instregex "^CLS(W|X)r$",
1357 (instregex "(CLS|CLZ|CNT)(v4i32|v8i16|v16i8)")>;
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| H A D | AArch64SchedThunderX3T110.td | 818 (instregex "^CLS(W|X)r$", "^CLZ(W|X)r$")>;
1464 (instregex "(CLS|CLZ|CNT)(v4i32|v8i16|v16i8)")>;
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| H A D | AArch64SchedA64FX.td | 945 def : InstRW<[A64FXWrite_2Cyc_GI0], (instregex "^CLS(W|X)r$",
1744 (instregex "(CLS|CLZ|CNT)(v4i32|v8i16|v16i8)")>;
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| H A D | AArch64InstrInfo.td | 1967 defm CLS : OneOperandData<0b101, "cls">;
4082 defm CLS : SIMDTwoVectorBHS<0, 0b00100, "cls", int_aarch64_neon_cls>;
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| /freebsd-13.1/contrib/llvm-project/clang/lib/Frontend/Rewrite/ |
| H A D | RewriteModernObjC.cpp | 6393 CLS = 0x0, enumerator
7108 flags = CLS; in RewriteObjCClassMetaData()
|