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Searched refs:CCR (Results 1 – 25 of 41) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrControl.td90 let Uses = [CCR] in {
149 let isBranch = 1, isTerminator = 1, Uses = [CCR] in
168 def : Pat<(MxBrCond bb:$target, !cast<PatLeaf>("MxCOND"#cc), CCR),
276 let Uses = [CCR], Defs = [CCR], isPseudo = 1 in {
286 } // Uses = [CCR], Defs = [CCR], isPseudo = 1
292 def : Pat<(i16 (sext (i8 (MxSetCC_C MxCONDcs, CCR)))), (SETCS_C16d)>;
299 def : Pat<(and (i8 (MxSetCC_C MxCONDcs, CCR)), 1), (SETd8cs)>;
302 def : Pat<(add (and (i8 (MxSetCC_C MxCONDcs, CCR)), 1), MxDRD8:$op),
308 def : Pat<(sub MxDRD8:$op, (and (i8 (MxSetCC_C MxCONDcs, CCR)), 1)),
314 def : Pat<(sub MxDRD8:$op, (i8 (MxSetCC_C MxCONDcs, CCR))),
[all …]
H A DM68kInstrBits.td51 let Defs = [CCR] in {
54 [(set CCR, (MxBt TYPE.VT:$dst, TYPE.VT:$bitno))],
59 [(set CCR, (MxBt TYPE.VT:$dst, TYPE.IPat:$bitno))],
65 [(set CCR, (MxBt (TYPE.Load MEMPat:$dst), TYPE.VT:$bitno))],
71 [(set CCR, (MxBt (TYPE.Load MEMPat:$dst), TYPE.IPat:$bitno))],
73 } // Defs = [CCR]
H A DM68kInstrArithmetic.td87 let Defs = [CCR] in {
173 } // Defs = [CCR]
306 let Uses = [CCR], Defs = [CCR] in {
368 let Defs = [CCR] in {
418 } // let Defs = [CCR]
480 let Defs = [CCR] in
514 let Defs = [CCR] in {
528 } // Defs = [CCR]
690 let Defs = [CCR] in {
701 let Uses = [CCR] in {
[all …]
H A DM68kInstrCompiler.td57 let usesCustomInserter = 1, Uses = [CCR] in
61 (TYPE.VT (MxCmov TYPE.VT:$t, TYPE.VT:$f, imm:$cond, CCR)))]>;
76 // sub / add which can clobber CCR.
77 let Defs = [SP, CCR], Uses = [SP] in {
123 let Defs = [SP, CCR], Uses = [SP] in
H A DM68kInstrInfo.td37 /* CCR */ SDTCisVT<1, i8>,
41 // RES, CCR <- op LHS, RHS
44 /* CCR */ SDTCisVT<1, i8>,
49 // RES, CCR <- op LHS, RHS, CCR
52 /* CCR */ SDTCisVT<1, i8>,
62 /* CCR */ SDTCisVT<1, i8>,
68 /* CCR */ SDTCisVT<0, i8>,
76 /* CCR */ SDTCisVT<4, i8>
82 /* CCR */ SDTCisVT<2, i8>
88 /* CCR */ SDTCisVT<2, i8>
[all …]
H A DM68kInstrShiftRotate.td71 let Defs = [CCR] in {
83 } // Defs = [CCR]
H A DM68kISelLowering.cpp2913 if (mi.readsRegister(M68k::CCR)) in checkAndUpdateCCRKill()
2915 if (mi.definesRegister(M68k::CCR)) in checkAndUpdateCCRKill()
2923 if (SBB->isLiveIn(M68k::CCR)) in checkAndUpdateCCRKill()
2928 SelectItr->addRegisterKilled(M68k::CCR, TRI); in checkAndUpdateCCRKill()
3028 Jcc1MBB->addLiveIn(M68k::CCR); in EmitLoweredSelect()
3043 Copy0MBB->addLiveIn(M68k::CCR); in EmitLoweredSelect()
3044 SinkMBB->addLiveIn(M68k::CCR); in EmitLoweredSelect()
3252 if (CCR.getOpcode() == M68kISD::ADD) { in combineCarryThroughADD()
3254 SDValue Carry = CCR.getOperand(0); in combineCarryThroughADD()
3291 SDValue CCR = N->getOperand(1); in combineM68kSetCC() local
[all …]
H A DM68kRegisterInfo.td76 def CCR : MxPseudoReg<"ccr">;
107 def CCRC : MxRegClass<[i8], 16, (add CCR)>;
H A DM68kInstrData.td59 let Defs = [CCR] in
482 // MOVE to/from SR/CCR
484 // A special care must be taken working with to/from CCR since it is basically
486 // instructions. Plus the original M68000 does not support moves from CCR. So in
487 // order to use CCR effectively one MUST use proper byte-size pseudo instructi-
497 let Defs = [CCR] in
514 /// Move from CCR
521 let Uses = [CCR] in
589 let Defs = [CCR] in {
H A DM68kInstrInfo.cpp682 bool FromCCR = SrcReg == M68k::CCR; in copyPhysReg()
684 bool ToCCR = DstReg == M68k::CCR; in copyPhysReg()
/freebsd-13.1/contrib/llvm-project/clang/lib/AST/
H A DComparisonCategories.cpp204 using CCR = ComparisonCategoryResult; in getPossibleResultsForType() typedef
205 std::vector<CCR> Values; in getPossibleResultsForType()
208 Values.push_back(IsStrong ? CCR::Equal : CCR::Equivalent); in getPossibleResultsForType()
209 Values.push_back(CCR::Less); in getPossibleResultsForType()
210 Values.push_back(CCR::Greater); in getPossibleResultsForType()
212 Values.push_back(CCR::Unordered); in getPossibleResultsForType()
/freebsd-13.1/contrib/llvm-project/clang/include/clang/AST/
H A DComparisonCategories.h153 using CCR = ComparisonCategoryResult; in makeWeakResult() local
154 if (!isStrong() && Res == CCR::Equal) in makeWeakResult()
155 return CCR::Equivalent; in makeWeakResult()
H A DExpr.h4967 const_child_range CCR = const_cast<const InitListExpr *>(this)->children(); in children() local
4968 return child_range(cast_away_const(CCR.begin()), in children()
4969 cast_away_const(CCR.end())); in children()
6196 const_child_range CCR = in children() local
6198 return child_range(cast_away_const(CCR.begin()), in children()
6199 cast_away_const(CCR.end())); in children()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RegisterBanks.td19 def CCRegBank : RegisterBank<"CC", [CCR]>;
H A DAArch64GenRegisterBankInfo.def217 PMI_None, // CCR
/freebsd-13.1/sys/dev/xdma/controller/
H A Dpl330.h51 #define CCR(n) (0x408 + 0x20 * (n)) /* Channel control for DMA channel n */ macro
/freebsd-13.1/sys/dev/pccard/
H A Dcard_if.m134 # Read the CCR register
144 # Write the CCR register
/freebsd-13.1/sys/kern/
H A Dtty_ttydisc.c68 #define CCR '\r' macro
74 (c) == CNL || (c) == CCR))
425 case CCR: in ttydisc_write_oproc()
1006 case CCR: in ttydisc_rint()
1014 c = CCR; in ttydisc_rint()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.td60 def CCR : RegisterClass<"Lanai", [i32], 32, (add SR)> {
/freebsd-13.1/sys/dev/cp/
H A Dcpddk.h85 unsigned char CCR, CSR, GMD, GLS, E1CS, E1CR, E1EPS; member
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/M68k/AsmParser/
H A DM68kAsmParser.cpp406 case M68k::CCR: in checkRegisterClass()
484 RegNo = M68k::CCR; in parseRegisterName()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.td421 def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>,
654 def CCROpnd : RegisterOperand<CCR> {
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td268 def CCR : RegisterClass<"AVR", [i8], 8, (add SREG)>
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp4881 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSignedALUO() local
5061 SDValue CCR = Cond.getOperand(3); in LowerSELECT() local
5144 ARMcc, CCR, Cmp); in getCMOV()
5460 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC() local
5681 Chain, Dest, ARMcc, CCR, Cmp); in LowerBR_CC()
5696 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC() local
5698 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp }; in LowerBR_CC()
6192 ARMcc, CCR, CmpLo); in LowerShiftRightParts()
6202 ARMcc, CCR, CmpHi); in LowerShiftRightParts()
6235 ARMcc, CCR, CmpHi); in LowerShiftLeftParts()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.td322 def CCR : RegisterClass<"SystemZ", [i32], 32, (add CC)>;

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