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Searched refs:BaseOpcode (Results 1 – 25 of 38) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrFMA3Info.cpp132 uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); in getFMA3Group() local
137 ((BaseOpcode >= 0x96 && BaseOpcode <= 0x9F) || in getFMA3Group()
138 (BaseOpcode >= 0xA6 && BaseOpcode <= 0xAF) || in getFMA3Group()
139 (BaseOpcode >= 0xB6 && BaseOpcode <= 0xBF)); in getFMA3Group()
156 unsigned FormIndex = ((BaseOpcode - 0x90) >> 4) & 0x3; in getFMA3Group()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DMIMGInstructions.td32 MIMGBaseOpcode BaseOpcode = !cast<MIMGBaseOpcode>(NAME);
60 let PrimaryKey = ["BaseOpcode"];
173 MIMGBaseOpcode BaseOpcode;
218 let d16 = !if(BaseOpcode.HasD16, ?, 0);
228 let d16 = !if(BaseOpcode.HasD16, ?, 0);
239 let d16 = !if(BaseOpcode.HasD16, ?, 0);
256 let d16 = !if(BaseOpcode.HasD16, ?, 0);
371 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME),
489 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME) in {
909 BaseOpcode = !cast<MIMGBaseOpcode>(NAME),
[all …]
H A DAMDGPUInstrInfo.h52 unsigned BaseOpcode; member
79 const ImageDimIntrinsicInfo *getImageDimInstrinsicByBaseOpcode(unsigned BaseOpcode,
H A DAMDGPUInstructionSelector.cpp1510 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = in selectImageIntrinsic() local
1518 unsigned IntrOpcode = Intr->BaseOpcode; in selectImageIntrinsic()
1529 if (!BaseOpcode->Sampler) in selectImageIntrinsic()
1552 if (BaseOpcode->Atomic) { in selectImageIntrinsic()
1558 const bool Is64Bit = BaseOpcode->AtomicX2 ? in selectImageIntrinsic()
1562 if (BaseOpcode->AtomicX2) { in selectImageIntrinsic()
1585 if (BaseOpcode->Store) { in selectImageIntrinsic()
1631 if (BaseOpcode->Atomic) in selectImageIntrinsic()
1684 if (BaseOpcode->AtomicX2) { in selectImageIntrinsic()
1714 if (BaseOpcode->Sampler) in selectImageIntrinsic()
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H A DAMDGPULegalizerInfo.cpp4262 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = in legalizeImageIntrinsic() local
4263 AMDGPU::getMIMGBaseOpcodeInfo(Intr->BaseOpcode); in legalizeImageIntrinsic()
4281 if (!BaseOpcode->Atomic) { in legalizeImageIntrinsic()
4283 if (BaseOpcode->Gather4) { in legalizeImageIntrinsic()
4287 } else if (!IsTFE && !BaseOpcode->Store) { in legalizeImageIntrinsic()
4312 if (BaseOpcode->Atomic) { in legalizeImageIntrinsic()
4320 if (BaseOpcode->AtomicX2) { in legalizeImageIntrinsic()
4334 AMDGPU::getMIMGLZMappingInfo(Intr->BaseOpcode)) { in legalizeImageIntrinsic()
4357 if (AMDGPU::getMIMGMIPMappingInfo(Intr->BaseOpcode)) { in legalizeImageIntrinsic()
4371 if (BaseOpcode->Gradients && !ST.hasG16() && (IsA16 != IsG16)) { in legalizeImageIntrinsic()
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H A DSIISelLowering.cpp1088 if (!BaseOpcode->Gather4) { in getTgtMemIntrinsic()
6043 if (BaseOpcode->Atomic) { in lowerImage()
6047 if (BaseOpcode->AtomicX2) { in lowerImage()
6067 if (BaseOpcode->Store) { in lowerImage()
6224 if (!BaseOpcode->Sampler) { in lowerImage()
6279 if (BaseOpcode->Atomic) in lowerImage()
6285 if (BaseOpcode->Store || BaseOpcode->Atomic) in lowerImage()
6292 if (BaseOpcode->Sampler) in lowerImage()
6311 if (BaseOpcode->HasD16) in lowerImage()
6349 if (BaseOpcode->AtomicX2) { in lowerImage()
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H A DBUFInstructions.td77 Instruction BaseOpcode = !cast<Instruction>(MTBUFGetBaseOpcode<NAME>.ret);
314 Instruction BaseOpcode = !cast<Instruction>(MUBUFGetBaseOpcode<NAME>.ret);
2618 "Opcode", "BaseOpcode", "elements", "has_vaddr", "has_srsrc", "has_soffset",
2633 let Key = ["BaseOpcode", "elements"];
2639 let Fields = ["Opcode", "BaseOpcode", "elements", "has_vaddr", "has_srsrc", "has_soffset"];
2652 let Key = ["BaseOpcode", "elements"];
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsInstrFPU.td260 let BaseOpcode = "RECIP_D32";
272 let BaseOpcode = "RSQRT_D32";
283 let BaseOpcode = "LDC132";
297 let BaseOpcode = "c.f."#NAME;
302 let BaseOpcode = "c.un."#NAME;
307 let BaseOpcode = "c.eq."#NAME;
312 let BaseOpcode = "c.ueq."#NAME;
317 let BaseOpcode = "c.olt."#NAME;
333 let BaseOpcode = "c.sf."#NAME;
351 let BaseOpcode = "c.lt."#NAME;
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H A DMipsEVAInstrInfo.td61 string BaseOpcode = instr_asm;
80 string BaseOpcode = instr_asm;
97 string BaseOpcode = instr_asm;
115 string BaseOpcode = instr_asm;
131 string BaseOpcode = instr_asm;
145 string BaseOpcode = instr_asm;
171 string BaseOpcode = instr_asm;
H A DMipsDSPInstrInfo.td274 string BaseOpcode = instr_asm;
285 string BaseOpcode = instr_asm;
296 string BaseOpcode = instr_asm;
307 string BaseOpcode = instr_asm;
319 string BaseOpcode = instr_asm;
330 string BaseOpcode = instr_asm;
341 string BaseOpcode = instr_asm;
351 string BaseOpcode = instr_asm;
363 string BaseOpcode = instr_asm;
374 string BaseOpcode = instr_asm;
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H A DMipsInstrFPU.td288 let BaseOpcode = "c.f."#NAME;
293 let BaseOpcode = "c.un."#NAME;
298 let BaseOpcode = "c.eq."#NAME;
303 let BaseOpcode = "c.ueq."#NAME;
324 let BaseOpcode = "c.sf."#NAME;
342 let BaseOpcode = "c.lt."#NAME;
350 let BaseOpcode = "c.le."#NAME;
397 let BaseOpcode = "RECIP_D32";
407 let BaseOpcode = "RSQRT_D32";
608 let BaseOpcode = "LDC164";
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H A DMicroMips32r6InstrInfo.td614 string BaseOpcode = opstr;
664 string BaseOpcode = opstr;
677 string BaseOpcode = opstr;
688 string BaseOpcode = opstr;
700 string BaseOpcode = opstr;
722 string BaseOpcode = opstr;
735 string BaseOpcode = opstr;
744 string BaseOpcode = opstr;
789 string BaseOpcode = opstr;
803 string BaseOpcode = opstr;
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H A DMipsDSPInstrFormats.td13 // Instructions with the same BaseOpcode and isNVStore values form a row.
14 let RowFields = ["BaseOpcode"];
49 string BaseOpcode = opstr;
H A DMipsInstrFormats.td42 // Instructions with the same BaseOpcode and isNVStore values form a row.
43 let RowFields = ["BaseOpcode"];
56 // Instructions with the same BaseOpcode and isNVStore values form a row.
57 let RowFields = ["BaseOpcode"];
119 string BaseOpcode = opstr;
H A DMips32r6InstrFormats.td17 // Instructions with the same BaseOpcode and isNVStore values form a row.
18 let RowFields = ["BaseOpcode"];
29 string BaseOpcode = opstr;
H A DMicroMipsInstrInfo.td217 let BaseOpcode = opstr;
228 let BaseOpcode = opstr;
270 string BaseOpcode = opstr;
286 string BaseOpcode = opstr;
592 let BaseOpcode = opstr;
597 let BaseOpcode = opstr;
604 let BaseOpcode = opstr;
611 let BaseOpcode = opstr;
H A DMicroMipsDSPInstrFormats.td13 string BaseOpcode = opstr;
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp1455 emitByte(BaseOpcode, OS); in encodeInstruction()
1476 emitByte(BaseOpcode, OS); in encodeInstruction()
1483 emitByte(BaseOpcode, OS); in encodeInstruction()
1491 emitByte(BaseOpcode, OS); in encodeInstruction()
1504 emitByte(BaseOpcode, OS); in encodeInstruction()
1520 emitByte(BaseOpcode, OS); in encodeInstruction()
1536 emitByte(BaseOpcode, OS); in encodeInstruction()
1556 emitByte(BaseOpcode, OS); in encodeInstruction()
1566 emitByte(BaseOpcode, OS); in encodeInstruction()
1602 emitByte(BaseOpcode, OS); in encodeInstruction()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagon.td162 // Instructions with the same BaseOpcode and isNVStore values form a row.
163 let RowFields = ["BaseOpcode", "isNVStore", "PNewValue", "isBrTaken", "isNT"];
178 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
190 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
202 let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];
214 let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];
226 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
238 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
320 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
328 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
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H A DHexagonDepInstrInfo.td53 let BaseOpcode = "A2_add";
217 let BaseOpcode = "A2_addi";
303 let BaseOpcode = "A2_and";
344 let BaseOpcode = "A2_aslh";
588 let BaseOpcode = "A2_or";
632 let BaseOpcode = "A2_add";
649 let BaseOpcode = "A2_add";
832 let BaseOpcode = "A2_or";
847 let BaseOpcode = "A2_or";
860 let BaseOpcode = "A2_or";
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H A DHexagonPseudo.td168 let BaseOpcode = "call";
200 BaseOpcode = "PS_call_nr", isExtentSigned = 1, opExtentAlign = 2 in
298 isBarrier = 1, BaseOpcode = "JMPret" in {
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.cpp138 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, in getMIMGOpcode() argument
147 return Info ? getMIMGBaseOpcodeInfo(Info->BaseOpcode) : nullptr; in getMIMGBaseOpcode()
158 unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode, in getAddrSizeMIMGOp() argument
161 unsigned AddrWords = BaseOpcode->NumExtraArgs; in getAddrSizeMIMGOp()
163 (BaseOpcode->LodOrClampOrMip ? 1 : 0); in getAddrSizeMIMGOp()
174 if (BaseOpcode->Gradients) { in getAddrSizeMIMGOp()
175 if ((IsA16 && !IsG16Supported) || BaseOpcode->G16) in getAddrSizeMIMGOp()
188 uint16_t BaseOpcode; member
198 uint16_t BaseOpcode; member
231 return Info ? Info->BaseOpcode : -1; in getMTBUFBaseOpcode()
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H A DAMDGPUBaseInfo.h281 MIMGBaseOpcode BaseOpcode; member
298 const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
344 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
351 unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode,
357 uint16_t BaseOpcode; member
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrFormats.td113 string BaseOpcode = "";
458 let BaseOpcode = "ld_rs9";
469 let BaseOpcode = "ld_rs9";
495 let BaseOpcode = "ld_limm";
525 let BaseOpcode = "ld_rlimm";
549 let BaseOpcode = "st_rs9";
560 let BaseOpcode = "st_rs9";
585 let BaseOpcode = "st_limm";
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp720 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = in convertMIMGInst() local
721 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); in convertMIMGInst()
727 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); in convertMIMGInst()
757 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); in convertMIMGInst()

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