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Searched refs:BaseOffs (Results 1 – 20 of 20) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp2473 if (BaseOffs != other.BaseOffs) in compare()
2546 BaseOffs = 0; in SetCombinedField()
2574 if (BaseOffs) { in print()
2576 << BaseOffs; in print()
3937 if (AddrMode.BaseOffs) { in matchScaledValue()
4606 AddrMode.BaseOffs += ConstantOffset; in matchOperationAddr()
4636 AddrMode.BaseOffs -= ConstantOffset; in matchOperationAddr()
4645 AddrMode.BaseOffs += ConstantOffset; in matchOperationAddr()
4672 AddrMode.BaseOffs += ConstantOffset; in matchOperationAddr()
5338 if (AddrMode.BaseOffs) { in optimizeMemoryInst()
[all …]
H A DTargetLoweringBase.cpp1930 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) in isLegalAddressingMode()
1942 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
1947 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1887 return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs); in isLegalAddressingMode()
1892 AM.BaseOffs%4 == 0; in isLegalAddressingMode()
1899 return isImmUs(AM.BaseOffs); in isLegalAddressingMode()
1902 return AM.Scale == 1 && AM.BaseOffs == 0; in isLegalAddressingMode()
1907 return isImmUs2(AM.BaseOffs); in isLegalAddressingMode()
1910 return AM.Scale == 2 && AM.BaseOffs == 0; in isLegalAddressingMode()
1914 return isImmUs4(AM.BaseOffs); in isLegalAddressingMode()
1917 return AM.Scale == 4 && AM.BaseOffs == 0; in isLegalAddressingMode()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPerfHintAnalysis.cpp243 auto *Ptr = GetPointerBaseWithConstantOffset(GEP, AM.BaseOffs, *DL); in visit()
H A DSIISelLowering.cpp1276 return AM.BaseOffs == 0 && AM.Scale == 0; in isLegalFlatAddressingMode()
1280 (AM.BaseOffs == 0 || in isLegalFlatAddressingMode()
1282 AM.BaseOffs, AMDGPUAS::FLAT_ADDRESS, SIInstrFlags::FLAT)); in isLegalFlatAddressingMode()
1289 AM.BaseOffs, AMDGPUAS::GLOBAL_ADDRESS, in isLegalGlobalAddressingMode()
1318 if (!SIInstrInfo::isLegalMUBUFImmOffset(AM.BaseOffs)) in isLegalMUBUFAddressingMode()
1359 if (AM.BaseOffs % 4 != 0) in isLegalAddressingMode()
1371 if (!isUInt<8>(AM.BaseOffs / 4)) in isLegalAddressingMode()
1376 if (!isUInt<32>(AM.BaseOffs / 4)) in isLegalAddressingMode()
1380 if (!isUInt<20>(AM.BaseOffs)) in isLegalAddressingMode()
1401 if (!isUInt<16>(AM.BaseOffs)) in isLegalAddressingMode()
[all …]
H A DSILoadStoreOptimizer.cpp1929 AM.BaseOffs = Dist; in promoteConstantOffsetToImm()
1954 AM.BaseOffs = P.second - AnchorAddr.Offset; in promoteConstantOffsetToImm()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DBasicTTIImpl.h303 AM.BaseOffs = BaseOffset;
338 AM.BaseOffs = BaseOffset; in getScalingFactorCost()
H A DTargetLowering.h2351 int64_t BaseOffs = 0; member
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp4180 AM.BaseOffs = C2APIntVal.getSExtValue(); in reassociationCanBreakAddressingModePattern()
4192 AM.BaseOffs = CombinedValue; in reassociationCanBreakAddressingModePattern()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp3422 if (!isAligned(A, AM.BaseOffs)) in isLegalAddressingMode()
3425 if (!isInt<11>(AM.BaseOffs >> Log2(A))) in isLegalAddressingMode()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp860 int64_t Offs = AM.BaseOffs; in isLegalAddressingMode()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp733 if (AM.BaseOffs < 0) in isLegalAddressingMode()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp15910 if (Ty->isVectorTy() && AM.BaseOffs != 0 && !Subtarget.hasP9Vector()) in isLegalAddressingMode()
15914 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) in isLegalAddressingMode()
15926 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
15931 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp970 if (!isInt<20>(AM.BaseOffs)) in isLegalAddressingMode()
977 if (!SupportedAM.LongDisplacement && !isUInt<12>(AM.BaseOffs)) in isLegalAddressingMode()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp4295 return !AM.BaseOffs && !AM.HasBaseReg && !AM.Scale; in isLegalAddressingMode()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp1039 AM.BaseOffs = C2APIntVal.getSExtValue(); in reassociationCanBreakAddressingModePattern()
1047 AM.BaseOffs = CombinedValue; in reassociationCanBreakAddressingModePattern()
2081 AM.BaseOffs = Offset->getSExtValue(); in canFoldInAddressingMode()
2090 AM.BaseOffs = -Offset->getSExtValue(); in canFoldInAddressingMode()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp12077 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale) in isLegalAddressingMode()
12084 return AM.HasBaseReg && !AM.BaseOffs && in isLegalAddressingMode()
12099 int64_t Offset = AM.BaseOffs; in isLegalAddressingMode()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp926 if (!isInt<12>(AM.BaseOffs)) in isLegalAddressingMode()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp18422 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget)) in isLegalAddressingMode()
18434 if (AM.BaseOffs) in isLegalAddressingMode()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp31871 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr)) in isLegalAddressingMode()
31888 Subtarget.is64Bit() && (AM.BaseOffs || AM.Scale > 1)) in isLegalAddressingMode()