Searched refs:AssignedReg (Results 1 – 7 of 7) sorted by relevance
| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | InlineAsmLowering.cpp | 99 Register AssignedReg; in getRegistersForValue() local
101 std::tie(AssignedReg, RC) = TLI.getRegForInlineAsmConstraint( in getRegistersForValue()
127 if (AssignedReg) { in getRegistersForValue()
128 for (; *I != AssignedReg; ++I) in getRegistersForValue()
136 Register R = AssignedReg ? Register(*I) : RegInfo.createVirtualRegister(RC); in getRegistersForValue()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 607 unsigned AssignedReg = FuncInfo.ValueMap[I]; in SelectLoad() local
609 AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr; in SelectLoad()
1172 unsigned AssignedReg = FuncInfo.ValueMap[I]; in PPCMoveToIntReg() local
1174 AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr; in PPCMoveToIntReg()
1278 unsigned AssignedReg = FuncInfo.ValueMap[I]; in SelectBinaryIntOp() local
1280 (AssignedReg ? MRI.getRegClass(AssignedReg) : in SelectBinaryIntOp()
1923 unsigned AssignedReg = FuncInfo.ValueMap[I]; in SelectIntExt() local
1925 (AssignedReg ? MRI.getRegClass(AssignedReg) : in SelectIntExt()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUTargetTransformInfo.cpp | 930 Register AssignedReg; in isInlineAsmSourceOfDivergence() local
932 std::tie(AssignedReg, RC) = TLI->getRegForInlineAsmConstraint( in isInlineAsmSourceOfDivergence()
934 if (AssignedReg) { in isInlineAsmSourceOfDivergence()
937 RC = TRI->getPhysRegClass(AssignedReg); in isInlineAsmSourceOfDivergence()
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| H A D | SIISelLowering.cpp | 12239 unsigned AssignedReg; in requiresUniformRegister() local
12241 std::tie(AssignedReg, RC) = getRegForInlineAsmConstraint( in requiresUniformRegister()
12245 if (AssignedReg != 0 && SIRI->isSGPRReg(MRI, AssignedReg)) in requiresUniformRegister()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegAllocFast.cpp | 290 MCPhysReg AssignedReg, bool Kill, bool LiveOut);
419 MCPhysReg AssignedReg, bool Kill, bool LiveOut) { in spill() argument
421 << " in " << printReg(AssignedReg, TRI)); in spill()
426 TII->storeRegToStackSlot(*MBB, Before, AssignedReg, Kill, FI, &RC, TRI); in spill()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FastISel.cpp | 371 Register &AssignedReg = FuncInfo.ValueMap[I]; in updateValueMap() local
372 if (!AssignedReg) in updateValueMap()
374 AssignedReg = Reg; in updateValueMap()
375 else if (Reg != AssignedReg) { in updateValueMap()
378 FuncInfo.RegFixups[AssignedReg + i] = Reg + i; in updateValueMap()
382 AssignedReg = Reg; in updateValueMap()
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| H A D | SelectionDAGBuilder.cpp | 8280 unsigned AssignedReg; in GetRegistersForValue() local
8282 std::tie(AssignedReg, RC) = TLI.getRegForInlineAsmConstraint( in GetRegistersForValue()
8353 if (AssignedReg) { in GetRegistersForValue()
8354 for (; *I != AssignedReg; ++I) in GetRegistersForValue()
8360 Register R = AssignedReg ? Register(*I) : RegInfo.createVirtualRegister(RC); in GetRegistersForValue()
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