Home
last modified time | relevance | path

Searched refs:ArgRC (Results 1 – 5 of 5) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp784 const TargetRegisterClass *ArgRC; in passSpecialInputs() local
787 std::tie(OutgoingArg, ArgRC, ArgTy) = in passSpecialInputs()
796 assert(IncomingArgRC == ArgRC); in passSpecialInputs()
801 LI->loadInputValue(InputReg, MIRBuilder, IncomingArg, ArgRC, ArgTy); in passSpecialInputs()
820 const TargetRegisterClass *ArgRC; in passSpecialInputs() local
823 std::tie(OutgoingArg, ArgRC, ArgTy) = in passSpecialInputs()
826 std::tie(OutgoingArg, ArgRC, ArgTy) = in passSpecialInputs()
829 std::tie(OutgoingArg, ArgRC, ArgTy) = in passSpecialInputs()
H A DAMDGPULegalizerInfo.h95 const TargetRegisterClass *ArgRC, LLT ArgTy) const;
H A DAMDGPULegalizerInfo.cpp2801 const TargetRegisterClass *ArgRC, in loadInputValue() argument
2807 Register LiveIn = getFunctionLiveInPhysReg(B.getMF(), B.getTII(), SrcReg, *ArgRC, in loadInputValue()
2835 const TargetRegisterClass *ArgRC; in loadInputValue() local
2837 std::tie(Arg, ArgRC, ArgTy) = MFI->getPreloadedValue(ArgType); in loadInputValue()
2841 return loadInputValue(DstReg, B, Arg, ArgRC, ArgTy); in loadInputValue()
H A DSIISelLowering.cpp2762 const TargetRegisterClass *ArgRC; in passSpecialInputs() local
2765 std::tie(OutgoingArg, ArgRC, ArgTy) = in passSpecialInputs()
2775 assert(IncomingArgRC == ArgRC); in passSpecialInputs()
2778 EVT ArgVT = TRI->getSpillSize(*ArgRC) == 8 ? MVT::i64 : MVT::i32; in passSpecialInputs()
2782 InputReg = loadInputValue(DAG, ArgRC, ArgVT, DL, *IncomingArg); in passSpecialInputs()
2806 const TargetRegisterClass *ArgRC; in passSpecialInputs() local
2809 std::tie(OutgoingArg, ArgRC, Ty) = in passSpecialInputs()
2812 std::tie(OutgoingArg, ArgRC, Ty) = in passSpecialInputs()
2815 std::tie(OutgoingArg, ArgRC, Ty) = in passSpecialInputs()
2832 InputReg = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgX); in passSpecialInputs()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp16232 const TargetRegisterClass *ArgRC = in canMergeExpensiveCrossRegisterBankCopy() local
16235 if (ArgRC == ResRC || !TLI.isOperationLegal(ISD::LOAD, ResVT)) in canMergeExpensiveCrossRegisterBankCopy()
16243 if (!TRI || TRI->getCommonSubClass(ArgRC, ResRC)) in canMergeExpensiveCrossRegisterBankCopy()