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Searched refs:AddrReg (Results 1 – 25 of 25) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVExpandAtomicPseudoInsts.cpp223 Register AddrReg = MI.getOperand(2).getReg(); in doAtomicBinOpExpansion() local
234 .addReg(AddrReg); in doAtomicBinOpExpansion()
248 .addReg(AddrReg) in doAtomicBinOpExpansion()
300 .addReg(AddrReg); in doMaskedAtomicBinOpExpansion()
333 .addReg(AddrReg) in doMaskedAtomicBinOpExpansion()
440 .addReg(AddrReg); in expandAtomicMinMaxOp()
492 .addReg(AddrReg) in expandAtomicMinMaxOp()
548 .addReg(AddrReg); in expandAtomicCmpXchg()
557 .addReg(AddrReg) in expandAtomicCmpXchg()
570 .addReg(AddrReg); in expandAtomicCmpXchg()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsNaClELFStreamer.cpp101 void emitMask(unsigned AddrReg, unsigned MaskReg, in emitMask() argument
105 MaskInst.addOperand(MCOperand::createReg(AddrReg)); in emitMask()
106 MaskInst.addOperand(MCOperand::createReg(AddrReg)); in emitMask()
114 unsigned AddrReg = MI.getOperand(0).getReg(); in sandboxIndirectJump() local
117 emitMask(AddrReg, IndirectBranchMaskReg, STI); in sandboxIndirectJump()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCExpandPseudos.cpp62 unsigned AddrReg = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in ExpandStore() local
65 BuildMI(*SI.getParent(), SI, SI.getDebugLoc(), TII->get(AddOpc), AddrReg) in ExpandStore()
71 .addReg(AddrReg) in ExpandStore()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCCallLowering.cpp115 MachineInstrBuilder AddrReg = MIRBuilder.buildFrameIndex(FramePtr, FI); in getStackAddress() local
117 return AddrReg.getReg(0); in getStackAddress()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.cpp1103 unsigned AddrReg; in buildIndirectWrite() local
1106 case 0: AddrReg = R600::R600_AddrRegClass.getRegister(Address); break; in buildIndirectWrite()
1107 case 1: AddrReg = R600::R600_Addr_YRegClass.getRegister(Address); break; in buildIndirectWrite()
1108 case 2: AddrReg = R600::R600_Addr_ZRegClass.getRegister(Address); break; in buildIndirectWrite()
1109 case 3: AddrReg = R600::R600_Addr_WRegClass.getRegister(Address); break; in buildIndirectWrite()
1116 AddrReg, ValueReg) in buildIndirectWrite()
1135 unsigned AddrReg; in buildIndirectRead() local
1138 case 0: AddrReg = R600::R600_AddrRegClass.getRegister(Address); break; in buildIndirectRead()
1139 case 1: AddrReg = R600::R600_Addr_YRegClass.getRegister(Address); break; in buildIndirectRead()
1140 case 2: AddrReg = R600::R600_Addr_ZRegClass.getRegister(Address); break; in buildIndirectRead()
[all …]
H A DSILoadStoreOptimizer.cpp110 const MachineOperand *AddrReg[MaxAddressRegs]; member
118 if (AddrReg[i]->isImm() || AddrRegNext.isImm()) { in hasSameBaseAddress()
138 const MachineOperand *AddrOp = AddrReg[i]; in hasMergeableAddress()
563 AddrReg[J] = &I->getOperand(AddrIdx[J]); in setMI()
1083 Register BaseReg = AddrReg->getReg(); in mergeRead2Pair()
1084 unsigned BaseSubReg = AddrReg->getSubReg(); in mergeRead2Pair()
1096 .addReg(AddrReg->getReg(), 0, BaseSubReg) in mergeRead2Pair()
1153 const MachineOperand *AddrReg = in mergeWrite2Pair() local
1177 Register BaseReg = AddrReg->getReg(); in mergeWrite2Pair()
1178 unsigned BaseSubReg = AddrReg->getSubReg(); in mergeWrite2Pair()
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H A DAMDGPUCallLowering.cpp99 auto AddrReg = MIRBuilder.buildFrameIndex( in getStackAddress() local
102 return AddrReg.getReg(0); in getStackAddress()
200 auto AddrReg = MIRBuilder.buildPtrAdd(PtrTy, SPReg, OffsetReg); in getStackAddress() local
202 return AddrReg.getReg(0); in getStackAddress()
H A DAMDGPULegalizerInfo.cpp4168 Register AddrReg = SrcOp.getReg(); in packImage16bitOpsToDwords() local
4174 AddrReg = B.buildBitcast(V2S16, AddrReg).getReg(0); in packImage16bitOpsToDwords()
4175 PackedAddrs.push_back(AddrReg); in packImage16bitOpsToDwords()
4188 B.buildBuildVector(V2S16, {AddrReg, B.buildUndef(S16).getReg(0)}) in packImage16bitOpsToDwords()
4193 V2S16, {AddrReg, MI.getOperand(ArgOffset + I + 1).getReg()}) in packImage16bitOpsToDwords()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/M68k/GlSel/
H A DM68kCallLowering.cpp142 MachineInstrBuilder AddrReg = MIRBuilder.buildFrameIndex(FramePtr, FI); in getStackAddress() local
144 return AddrReg.getReg(0); in getStackAddress()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SIMDInstrOpt.cpp507 unsigned SeqReg, AddrReg; in optimizeLdStInterleave() local
521 AddrReg = MI.getOperand(1).getReg(); in optimizeLdStInterleave()
575 .addReg(AddrReg) in optimizeLdStInterleave()
615 .addReg(AddrReg) in optimizeLdStInterleave()
620 .addReg(AddrReg) in optimizeLdStInterleave()
H A DAArch64ExpandPseudoInsts.cpp196 Register AddrReg = MI.getOperand(2).getReg(); in expandCMP_SWAP() local
218 .addReg(AddrReg); in expandCMP_SWAP()
235 .addReg(AddrReg); in expandCMP_SWAP()
276 Register AddrReg = MI.getOperand(3).getReg(); in expandCMP_SWAP_128() local
324 .addReg(AddrReg); in expandCMP_SWAP_128()
353 .addReg(AddrReg); in expandCMP_SWAP_128()
367 .addReg(AddrReg); in expandCMP_SWAP_128()
H A DAArch64FastISel.cpp229 bool emitStoreRelease(MVT VT, unsigned SrcReg, unsigned AddrReg,
2037 unsigned AddrReg, in emitStoreRelease() argument
2050 AddrReg = constrainOperandRegClass(II, AddrReg, 1); in emitStoreRelease()
2053 .addReg(AddrReg) in emitStoreRelease()
2177 unsigned AddrReg = getRegForValue(PtrV); in selectStore() local
2178 return emitStoreRelease(VT, SrcReg, AddrReg, in selectStore()
2496 unsigned AddrReg = getRegForValue(BI->getOperand(0)); in selectIndirectBr() local
2497 if (AddrReg == 0) in selectIndirectBr()
2502 AddrReg = constrainOperandRegClass(II, AddrReg, II.getNumDefs()); in selectIndirectBr()
4986 const unsigned AddrReg = constrainOperandRegClass( in selectAtomicCmpXchg() local
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallLowering.cpp101 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress() local
104 return AddrReg.getReg(0); in getStackAddress()
H A DX86SpeculativeLoadHardening.cpp1162 Register AddrReg = MRI->createVirtualRegister(&X86::GR64RegClass); in tracePredStateThroughIndirectBranches() local
1164 BuildMI(MBB, InsertPt, DebugLoc(), TII->get(X86::LEA64r), AddrReg) in tracePredStateThroughIndirectBranches()
1175 .addReg(AddrReg, RegState::Kill); in tracePredStateThroughIndirectBranches()
H A DX86InstructionSelector.cpp1409 Register AddrReg = MRI.createVirtualRegister(&X86::GR64RegClass); in materializeFP() local
1410 BuildMI(*I.getParent(), I, DbgLoc, TII.get(X86::MOV64ri), AddrReg) in materializeFP()
1419 AddrReg) in materializeFP()
H A DX86FastISel.cpp3776 Register AddrReg = createResultReg(&X86::GR64RegClass); in X86MaterializeFP() local
3778 AddrReg) in X86MaterializeFP()
3782 addRegReg(MIB, AddrReg, false, PICBase, false); in X86MaterializeFP()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp145 auto AddrReg = MIRBuilder.buildFrameIndex(LLT::pointer(0, 64), FI); in getStackAddress() local
146 return AddrReg.getReg(0); in getStackAddress()
255 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress() local
258 return AddrReg.getReg(0); in getStackAddress()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp105 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress() local
108 return AddrReg.getReg(0); in getStackAddress()
H A DARMExpandPseudoInsts.cpp1641 Register AddrReg = MI.getOperand(2).getReg(); in ExpandCMP_SWAP() local
1679 MIB.addReg(AddrReg); in ExpandCMP_SWAP()
1703 .addReg(AddrReg); in ExpandCMP_SWAP()
1769 Register AddrReg = MI.getOperand(2).getReg(); in ExpandCMP_SWAP_64() local
1797 MIB.addReg(AddrReg).add(predOps(ARMCC::AL)); in ExpandCMP_SWAP_64()
1826 MIB.addReg(AddrReg).add(predOps(ARMCC::AL)); in ExpandCMP_SWAP_64()
H A DARMFastISel.cpp1318 unsigned AddrReg = getRegForValue(I->getOperand(0)); in SelectIndirectBr() local
1319 if (AddrReg == 0) return false; in SelectIndirectBr()
1325 TII.get(Opc)).addReg(AddrReg)); in SelectIndirectBr()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp235 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress() local
236 return AddrReg.getReg(0); in getStackAddress()
H A DMipsISelLowering.cpp2546 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0; in lowerEH_RETURN() local
2548 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1)); in lowerEH_RETURN()
2551 DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())), in lowerEH_RETURN()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp1859 unsigned AddrReg = getRegForValue(I->getOperand(0)); in SelectIndirectBr() local
1860 if (AddrReg == 0) in SelectIndirectBr()
1864 .addReg(AddrReg); in SelectIndirectBr()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.cpp749 unsigned AddrReg = MI->getOperand(OpNum++).getReg(); in printInst() local
750 O << ", [" << getRegisterName(AddrReg) << ']'; in printInst()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp4074 Register AddrReg = LdStMI.getPointerReg(); in reduceLoadStoreWidth() local
4100 LLT PtrTy = MRI.getType(AddrReg); in reduceLoadStoreWidth()
4119 MIRBuilder.materializePtrAdd(NewAddrReg, AddrReg, OffsetTy, ByteOffset); in reduceLoadStoreWidth()