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Searched refs:tiling_flags (Results 1 – 17 of 17) sorted by relevance

/freebsd-12.1/sys/dev/drm2/radeon/
H A Dradeon_object.c392 lobj->tiling_flags = bo->tiling_flags; in radeon_bo_list_validate()
416 if (!bo->tiling_flags) in radeon_bo_get_surface_reg()
455 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, in radeon_bo_get_surface_reg()
477 uint32_t tiling_flags, uint32_t pitch) in radeon_bo_set_tiling_flags() argument
485 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; in radeon_bo_set_tiling_flags()
486 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; in radeon_bo_set_tiling_flags()
530 bo->tiling_flags = tiling_flags; in radeon_bo_set_tiling_flags()
537 uint32_t *tiling_flags, in radeon_bo_get_tiling_flags() argument
542 if (tiling_flags) in radeon_bo_get_tiling_flags()
543 *tiling_flags = bo->tiling_flags; in radeon_bo_get_tiling_flags()
[all …]
H A Dradeon_fb.c114 u32 tiling_flags = 0; in radeonfb_create_pinned_object() local
142 tiling_flags = RADEON_TILING_MACRO; in radeonfb_create_pinned_object()
147 tiling_flags |= RADEON_TILING_SWAP_32BIT; in radeonfb_create_pinned_object()
150 tiling_flags |= RADEON_TILING_SWAP_16BIT; in radeonfb_create_pinned_object()
156 if (tiling_flags) { in radeonfb_create_pinned_object()
158 tiling_flags | RADEON_TILING_SURFACE, in radeonfb_create_pinned_object()
H A Dradeon_object.h147 u32 tiling_flags, u32 pitch);
149 u32 *tiling_flags, u32 *pitch);
H A Dr300.c690 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
692 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
694 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
759 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
761 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
763 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
844 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
846 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
848 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
H A Dr200.c222 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) in r200_packet0_check()
224 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) in r200_packet0_check()
294 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) in r200_packet0_check()
296 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) in r200_packet0_check()
H A Dradeon_legacy_crtc.c385 uint32_t tiling_flags; in radeon_crtc_do_set_base() local
439 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in radeon_crtc_do_set_base()
441 if (tiling_flags & RADEON_TILING_MICRO) in radeon_crtc_do_set_base()
459 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_do_set_base()
475 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_do_set_base()
H A Datombios_crtc.c1076 uint32_t fb_format, fb_pitch_pixels, tiling_flags; in dce4_crtc_do_set_base() local
1116 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in dce4_crtc_do_set_base()
1149 if (tiling_flags & RADEON_TILING_MACRO) { in dce4_crtc_do_set_base()
1172 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); in dce4_crtc_do_set_base()
1177 } else if (tiling_flags & RADEON_TILING_MICRO) in dce4_crtc_do_set_base()
1279 uint32_t fb_format, fb_pitch_pixels, tiling_flags; in avivo_crtc_do_set_base() local
1317 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in avivo_crtc_do_set_base()
1355 if (tiling_flags & RADEON_TILING_MACRO) in avivo_crtc_do_set_base()
1357 else if (tiling_flags & RADEON_TILING_MICRO) in avivo_crtc_do_set_base()
1360 if (tiling_flags & RADEON_TILING_MACRO) in avivo_crtc_do_set_base()
[all …]
H A Devergreen_cs.c99 static u32 evergreen_cs_get_aray_mode(u32 tiling_flags) in evergreen_cs_get_aray_mode() argument
101 if (tiling_flags & RADEON_TILING_MACRO) in evergreen_cs_get_aray_mode()
103 else if (tiling_flags & RADEON_TILING_MICRO) in evergreen_cs_get_aray_mode()
1397 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_check_reg()
1400 evergreen_tiling_fields(reloc->lobj.tiling_flags, in evergreen_cs_check_reg()
1660 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_check_reg()
1663 evergreen_tiling_fields(reloc->lobj.tiling_flags, in evergreen_cs_check_reg()
1688 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_check_reg()
1691 evergreen_tiling_fields(reloc->lobj.tiling_flags, in evergreen_cs_check_reg()
2499 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { in evergreen_packet3_check()
[all …]
H A Dr100.c1271 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) in r100_reloc_pitch_offset()
1724 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) in r100_packet0_check()
1726 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) in r100_packet0_check()
3197 uint32_t tiling_flags, uint32_t pitch, in r100_set_surface_reg() argument
3207 if (tiling_flags & RADEON_TILING_MACRO) in r100_set_surface_reg()
3210 if (tiling_flags & (RADEON_TILING_MACRO)) in r100_set_surface_reg()
3212 if (tiling_flags & RADEON_TILING_MICRO) in r100_set_surface_reg()
3215 if (tiling_flags & RADEON_TILING_MACRO) in r100_set_surface_reg()
3217 if (tiling_flags & RADEON_TILING_MICRO) in r100_set_surface_reg()
3221 if (tiling_flags & RADEON_TILING_SWAP_16BIT) in r100_set_surface_reg()
[all …]
H A Dr600_cs.c1127 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { in r600_cs_check_reg()
1226 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { in r600_cs_check_reg()
1229 } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { in r600_cs_check_reg()
1557 u32 tiling_flags) in r600_check_texture_resource() argument
1579 if (tiling_flags & RADEON_TILING_MACRO) in r600_check_texture_resource()
1581 else if (tiling_flags & RADEON_TILING_MICRO) in r600_check_texture_resource()
2047 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) in r600_packet3_check()
2049 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) in r600_packet3_check()
2065 reloc->lobj.tiling_flags); in r600_packet3_check()
H A Dradeon_gem.c417 r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch); in radeon_gem_set_tiling_ioctl()
438 radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch); in radeon_gem_get_tiling_ioctl()
H A Dradeon_drm.h830 uint32_t tiling_flags; member
836 uint32_t tiling_flags; member
H A Dradeon_asic.h94 uint32_t tiling_flags, uint32_t pitch,
328 uint32_t tiling_flags, uint32_t pitch,
H A Dradeon.h215 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
344 u32 tiling_flags; member
366 u32 tiling_flags; member
1262 uint32_t tiling_flags, uint32_t pitch,
H A Dradeon_display.c362 u32 tiling_flags, pitch_pixels; in radeon_crtc_page_flip() local
420 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in radeon_crtc_page_flip()
428 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_page_flip()
H A Devergreen.c61 void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, in evergreen_tiling_fields() argument
65 *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; in evergreen_tiling_fields()
66 *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; in evergreen_tiling_fields()
67 …*mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TI… in evergreen_tiling_fields()
68 …*tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MA… in evergreen_tiling_fields()
H A Dr600.c2770 uint32_t tiling_flags, uint32_t pitch, in r600_set_surface_reg() argument