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Searched refs:sub2 (Results 1 – 20 of 20) sorted by relevance

/freebsd-12.1/contrib/amd/amd/
H A Dsun_map.c280 char *sub = NULL, *sub2 = NULL, *out = NULL; in sun_append_str() local
300 if ((sub2 = sun_expand2amd(sub)) != NULL) { in sun_append_str()
301 out = sub2; in sun_append_str()
316 XFREE(sub2); in sun_append_str()
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DAMDGPURegisterInfo.cpp32 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, AMDGPU::sub4, in getSubRegFromChannel()
H A DSIRegisterInfo.td16 list<SubRegIndex> ret3 = [sub0, sub1, sub2];
17 list<SubRegIndex> ret4 = [sub0, sub1, sub2, sub3];
18 list<SubRegIndex> ret8 = [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7];
19 list<SubRegIndex> ret16 = [sub0, sub1, sub2, sub3,
H A DSIRegisterInfo.cpp1400 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, in getRegSplitParts()
1407 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, in getRegSplitParts()
1412 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, in getRegSplitParts()
1416 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, in getRegSplitParts()
H A DR600MachineScheduler.cpp265 case R600::sub2: in getAluKind()
H A DR600RegisterInfo.td23 let SubRegIndices = [sub0, sub1, sub2, sub3];
H A DR600Instructions.td1705 def : Extract_Element <f32, v4f32, 2, sub2>;
1710 def : Insert_Element <f32, v4f32, 2, sub2>;
1715 def : Extract_Element <i32, v4i32, 2, sub2>;
1720 def : Insert_Element <i32, v4i32, 2, sub2>;
H A DSILoadStoreOptimizer.cpp972 return std::make_pair(AMDGPU::sub2, AMDGPU::sub0_sub1); in getSubRegIdxs()
1013 return std::make_pair(AMDGPU::sub0_sub1, AMDGPU::sub2); in getSubRegIdxs()
H A DSIFrameLowering.cpp439 unsigned Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2); in emitEntryFunctionScratchSetup()
H A DSIInstrInfo.cpp1892 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, in insertSelect()
3726 .addReg(VRsrc, VRsrcUndef, AMDGPU::sub2); in emitLoadSRsrcFromVGPRLoop()
3736 .addImm(AMDGPU::sub2) in emitLoadSRsrcFromVGPRLoop()
3874 .addImm(AMDGPU::sub2) in extractRsrcPtr()
H A DSIISelLowering.cpp9017 case AMDGPU::sub2: return 2; in SubIdx2Lane()
9171 case AMDGPU::sub1: Idx = AMDGPU::sub2; break; in adjustWritemask()
9172 case AMDGPU::sub2: Idx = AMDGPU::sub3; break; in adjustWritemask()
9422 DAG.getTargetConstant(AMDGPU::sub2, DL, MVT::i32), in buildRSRC()
/freebsd-12.1/contrib/gcc/
H A Dloop-invariant.c317 rtx sub1, sub2; in invariant_expr_equal_p() local
362 sub2 = XEXP (e2, i); in invariant_expr_equal_p()
364 if (!invariant_expr_equal_p (insn1, sub1, insn2, sub2)) in invariant_expr_equal_p()
376 sub2 = XVECEXP (e2, i, j); in invariant_expr_equal_p()
378 if (!invariant_expr_equal_p (insn1, sub1, insn2, sub2)) in invariant_expr_equal_p()
/freebsd-12.1/contrib/file/magic/Magdir/
H A Dicc71 # Profile version major.4bit-minor.sub1.sub2 like 4.3.0.0 (04300000h)
/freebsd-12.1/contrib/gcc/config/soft-fp/
H A Dop-common.h563 goto sub2; \
577 sub2: \
/freebsd-12.1/sys/contrib/zstd/lib/decompress/
H A Dzstd_decompress.c1128 int const sub2 = dec64table[sequence.offset]; in ZSTD_execSequence() local
1135 match -= sub2; in ZSTD_execSequence()
1208 int const sub2 = dec64table[sequence.offset]; in ZSTD_execSequenceLong() local
1215 match -= sub2; in ZSTD_execSequenceLong()
/freebsd-12.1/sys/contrib/zstd/lib/legacy/
H A Dzstd_v04.c2969 const int sub2 = dec64table[sequence.offset]; in ZSTD_execSequence() local
2976 match -= sub2; in ZSTD_execSequence()
H A Dzstd_v06.c3410 int const sub2 = dec64table[sequence.offset]; in ZSTDv06_execSequence() local
3417 match -= sub2; in ZSTDv06_execSequence()
H A Dzstd_v05.c3262 const int sub2 = dec64table[sequence.offset]; in ZSTDv05_execSequence() local
3269 match -= sub2; in ZSTDv05_execSequence()
H A Dzstd_v07.c3633 int const sub2 = dec64table[sequence.offset]; in ZSTDv07_execSequence() local
3640 match -= sub2; in ZSTDv07_execSequence()
/freebsd-12.1/contrib/llvm/lib/Target/ARC/
H A DARCInstrInfo.td226 defm SUB2 : ArcBinaryGEN4Inst<0b011000, "sub2">;