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/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonDepMapAsm2Intrin.td19 def: Pat<(int_hexagon_M2_mpysu_up IntRegs:$src1, IntRegs:$src2),
25 def: Pat<(int_hexagon_M2_cmpysc_s1 IntRegs:$src1, IntRegs:$src2),
27 def: Pat<(int_hexagon_M2_cmpysc_s0 IntRegs:$src1, IntRegs:$src2),
37 def: Pat<(int_hexagon_F2_sfmax IntRegs:$src1, IntRegs:$src2),
97 def: Pat<(int_hexagon_M2_mpyi IntRegs:$src1, IntRegs:$src2),
237 def: Pat<(int_hexagon_A2_sub IntRegs:$src1, IntRegs:$src2),
2045 def: Pat<(int_hexagon_V6_veqh HvxVR:$src1, HvxVR:$src2),
2245 def: Pat<(int_hexagon_V6_vxor HvxVR:$src1, HvxVR:$src2),
2329 def: Pat<(int_hexagon_V6_veqw HvxVR:$src1, HvxVR:$src2),
2449 def: Pat<(int_hexagon_V6_vand HvxVR:$src1, HvxVR:$src2),
[all …]
H A DHexagonMapAsm2IntrinV65.gen.td25 def: Pat<(int_hexagon_V6_vavguw HvxVR:$src1, HvxVR:$src2), (V6_vavguw HvxVR:$src1, HvxVR:$src2)>, R…
26 def: Pat<(int_hexagon_V6_vavguw_128B HvxVR:$src1, HvxVR:$src2), (V6_vavguw HvxVR:$src1, HvxVR:$src2…
27 …ef: Pat<(int_hexagon_V6_vavguwrnd HvxVR:$src1, HvxVR:$src2), (V6_vavguwrnd HvxVR:$src1, HvxVR:$src…
29 def: Pat<(int_hexagon_V6_vavgb HvxVR:$src1, HvxVR:$src2), (V6_vavgb HvxVR:$src1, HvxVR:$src2)>, Req…
30 def: Pat<(int_hexagon_V6_vavgb_128B HvxVR:$src1, HvxVR:$src2), (V6_vavgb HvxVR:$src1, HvxVR:$src2)>…
31 def: Pat<(int_hexagon_V6_vavgbrnd HvxVR:$src1, HvxVR:$src2), (V6_vavgbrnd HvxVR:$src1, HvxVR:$src2)…
33 …: Pat<(int_hexagon_V6_vlut4 HvxVR:$src1, DoubleRegs:$src2), (V6_vlut4 HvxVR:$src1, DoubleRegs:$src…
35 def: Pat<(int_hexagon_V6_vnavgb HvxVR:$src1, HvxVR:$src2), (V6_vnavgb HvxVR:$src1, HvxVR:$src2)>, R…
36 def: Pat<(int_hexagon_V6_vnavgb_128B HvxVR:$src1, HvxVR:$src2), (V6_vnavgb HvxVR:$src1, HvxVR:$src2…
37 …ef: Pat<(int_hexagon_V6_vmpabuu HvxWR:$src1, IntRegs:$src2), (V6_vmpabuu HvxWR:$src1, IntRegs:$src…
[all …]
H A DHexagonMapAsm2IntrinV62.gen.td11 def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
12 (MI HvxVR:$src1, IntRegs:$src2)>;
14 (MI HvxVR:$src1, IntRegs:$src2)>;
26 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2),
27 (MI HvxVR:$src1, HvxVR:$src2)>;
29 (MI HvxVR:$src1, HvxVR:$src2)>;
33 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2),
34 (MI HvxWR:$src1, HvxWR:$src2)>;
36 (MI HvxWR:$src1, HvxWR:$src2)>;
87 (MI HvxQR:$src1, HvxVR:$src2)>;
[all …]
H A DHexagonIntrinsicsV60.td120 (MI HvxWR:$src1, IntRegs:$src2)>;
128 (MI HvxVR:$src1, IntRegs:$src2)>;
132 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2),
133 (MI HvxWR:$src1, HvxVR:$src2)>;
136 (MI HvxWR:$src1, HvxVR:$src2)>;
140 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2),
144 (MI HvxWR:$src1, HvxWR:$src2)>;
148 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2),
152 (MI HvxVR:$src1, HvxVR:$src2)>;
164 def: Pat<(IntID HvxQR:$src1, HvxQR:$src2),
[all …]
H A DHexagonIntrinsics.td136 def : Pat <(int_hexagon_C2_cmplt I32:$src1, I32:$src2),
137 (C2_tfrpr (C2_cmpgt I32:$src2, I32:$src1))>;
138 def : Pat <(int_hexagon_C2_cmpltu I32:$src1, I32:$src2),
139 (C2_tfrpr (C2_cmpgtu I32:$src2, I32:$src1))>;
147 (OutputInst I32:$src1, I32:$src2, u4_0ImmPred:$src3,
208 def : Pat<(IntID HvxQR:$src1, IntRegs:$src2, HvxVR:$src3),
361 def: Pat<(IntID HvxVR:$src1, u3_0ImmPred:$src2),
371 def: Pat<(IntID HvxVR:$src1, u3_64_ImmPred:$src2),
373 (SUB_64_VAL u3_64_ImmPred:$src2))>,
395 (MI HvxVR:$src1, HvxVR:$src2,
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86InstrXOP.td175 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
182 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
252 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
260 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
302 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
310 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
318 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
349 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
357 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
364 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[all …]
H A DX86InstrSSE.td28 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
35 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
50 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
57 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
73 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
80 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
221 def : InstAlias<OpcodeStr#".s\t{$src2, $dst|$dst, $src2}",
6126 "vptest\t{$src2, $src1|$src1, $src2}",
6148 "ptest\t{$src2, $src1|$src1, $src2}",
6152 "ptest\t{$src2, $src1|$src1, $src2}",
[all …]
H A DX86InstrFMA.td43 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
51 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
64 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
71 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
84 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
184 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
192 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
205 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
395 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
402 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[all …]
H A DX86InstrShiftRotate.td35 "shl{b}\t{$src2, $dst|$dst, $src2}",
40 "shl{w}\t{$src2, $dst|$dst, $src2}",
44 "shl{l}\t{$src2, $dst|$dst, $src2}",
49 "shl{q}\t{$src2, $dst|$dst, $src2}",
139 "shr{b}\t{$src2, $dst|$dst, $src2}",
142 "shr{w}\t{$src2, $dst|$dst, $src2}",
146 "shr{l}\t{$src2, $dst|$dst, $src2}",
150 "shr{q}\t{$src2, $dst|$dst, $src2}",
241 "sar{b}\t{$src2, $dst|$dst, $src2}",
244 "sar{w}\t{$src2, $dst|$dst, $src2}",
[all …]
H A DX86InstrCompiler.td689 "{$src2, $dst|$dst, $src2}"),
696 "{$src2, $dst|$dst, $src2}"),
704 "{$src2, $dst|$dst, $src2}"),
712 "{$src2, $dst|$dst, $src2}"),
719 "{$src2, $dst|$dst, $src2}"),
726 "{$src2, $dst|$dst, $src2}"),
734 "{$src2, $dst|$dst, $src2}"),
742 "{$src2, $dst|$dst, $src2}"),
750 "{$src2, $dst|$dst, $src2}"),
758 "{$src2, $dst|$dst, $src2}"),
[all …]
H A DX86InstrCMovSetCC.td23 !strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"),
25 (X86cmov GR16:$src1, GR16:$src2, CondNode, EFLAGS))]>,
29 !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"),
31 (X86cmov GR32:$src1, GR32:$src2, CondNode, EFLAGS))]>,
35 !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"),
44 !strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"),
45 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
49 !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"),
50 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
54 !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"),
[all …]
H A DX86InstrAVX512.td2049 "$src2, $src1", "$src1, $src2",
2516 "$src2, $src1", "$src1, $src2",
2525 "$src2, $src1", "$src1, $src2",
4694 "$src2, $src1", "$src1, $src2",
5625 "$src2, $src1", "$src1, $src2",
5803 "$src2, $src1", "$src1, $src2",
5808 "$src2, $src1", "$src1, $src2",
5827 "$src2, $src1", "$src1, $src2",
5832 "$src2, $src1", "$src1, $src2",
12495 "$src3, $src2", "$src2, $src3",
[all …]
H A DX86InstrMMX.td40 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
47 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
59 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
64 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
70 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
99 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
104 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
117 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
122 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
544 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
[all …]
H A DX86InstrArithmetic.td156 "imul{w}\t{$src2, $dst|$dst, $src2}",
161 "imul{l}\t{$src2, $dst|$dst, $src2}",
167 "imul{q}\t{$src2, $dst|$dst, $src2}",
176 "imul{w}\t{$src2, $dst|$dst, $src2}",
182 "imul{l}\t{$src2, $dst|$dst, $src2}",
188 "imul{q}\t{$src2, $dst|$dst, $src2}",
645 mnemonic, "{$src2, $src1|$src1, $src2}", pattern>,
679 mnemonic, "{$src2, $dst|$dst, $src2}", []>,
695 mnemonic, "{$src2, $src1|$src1, $src2}", []>,
708 mnemonic, "{$src2, $src1|$src1, $src2}", pattern>,
[all …]
H A DX86InstrVMX.td20 def INVEPT32 : I<0x80, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
21 "invept\t{$src2, $src1|$src1, $src2}", []>, T8PD,
23 def INVEPT64 : I<0x80, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
24 "invept\t{$src2, $src1|$src1, $src2}", []>, T8PD,
28 def INVVPID32 : I<0x81, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
29 "invvpid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
31 def INVVPID64 : I<0x81, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
32 "invvpid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
H A DX86InstrMPX.td31 def 32rm: I<opc, MRMSrcMem, (outs), (ins BNDR:$src1, anymem:$src2),
32 OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
34 def 64rm: I<opc, MRMSrcMem, (outs), (ins BNDR:$src1, anymem:$src2),
35 OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
38 def 32rr: I<opc, MRMSrcReg, (outs), (ins BNDR:$src1, GR32:$src2),
39 OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
41 def 64rr: I<opc, MRMSrcReg, (outs), (ins BNDR:$src1, GR64:$src2),
42 OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
H A DX86InstrFragmentsSIMD.td798 (X86masked_gather node:$src1, node:$src2, node:$src3) , [{
804 (X86masked_gather node:$src1, node:$src2, node:$src3) , [{
810 (X86masked_gather node:$src1, node:$src2, node:$src3) , [{
815 (X86masked_gather node:$src1, node:$src2, node:$src3) , [{
820 (X86masked_gather node:$src1, node:$src2, node:$src3) , [{
825 (X86masked_gather node:$src1, node:$src2, node:$src3) , [{
831 (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{
837 (X86masked_scatter node:$src1, node:$src2, node:$src3) , [{
1043 PatFrag<(ops node:$src1, node:$src2, node:$src3),
1048 PatFrag<(ops node:$src1, node:$src2, node:$src3),
[all …]
H A DX86InstrInfo.td1744 "bt{w}\t{$src2, $src1|$src1, $src2}",
1748 "bt{l}\t{$src2, $src1|$src1, $src2}",
1752 "bt{q}\t{$src2, $src1|$src1, $src2}",
1765 "bt{w}\t{$src2, $src1|$src1, $src2}",
1768 "bt{l}\t{$src2, $src1|$src1, $src2}",
1771 "bt{q}\t{$src2, $src1|$src1, $src2}",
1777 "bt{w}\t{$src2, $src1|$src1, $src2}",
1781 "bt{l}\t{$src2, $src1|$src1, $src2}",
1785 "bt{q}\t{$src2, $src1|$src1, $src2}",
1793 "bt{w}\t{$src2, $src1|$src1, $src2}",
[all …]
/freebsd-12.1/contrib/cortex-strings/src/arm/
H A Dstrcmp.S82 #define src2 r1 macro
165 ldrb r3, [src2]
176 orr tmp1, src1, src2
194 bic src2, src2, #7
285 bic src2, src2, #3
298 sub src2, src2, tmp1
324 add src2, src2, #4
352 add src2, src2, #4
361 bic src2, src2, #3
428 ldrh data2, [src2]
[all …]
/freebsd-12.1/contrib/sendmail/libsm/
H A Db-strcmp.c56 char src1[SIZE], src2[SIZE]; local
88 (void) sm_strlcpy(src2, "1234567890", SIZE);
92 (void) sm_strlcpy(src2, "1234567891", SIZE);
96 (void) sm_strlcpy(src2, "1234567891", SIZE);
100 k, src1, src2);
108 j += strcasecmp(src1, src2);
119 j += sm_strcasecmp(src1, src2);
H A Dstrl.c148 sm_strlcat2(dst, src1, src2, len) in sm_strlcat2() argument
151 register const char *src2;
161 return o + strlen(src1) + strlen(src2);
174 return j + strlen(src1 + i) + strlen(src2);
180 for (i = 0; i < len && (dst[j] = src2[i]) != 0; i++, j++)
183 if (src2[i] == '\0')
186 return j + strlen(src2 + i);
/freebsd-12.1/contrib/llvm/include/llvm/Target/
H A DGenericOpcodes.td68 let InOperandList = (ins unknown:$src2);
178 let InOperandList = (ins type0:$src1, type0:$src2);
186 let InOperandList = (ins type0:$src1, type0:$src2);
194 let InOperandList = (ins type0:$src1, type0:$src2);
202 let InOperandList = (ins type0:$src1, type0:$src2);
210 let InOperandList = (ins type0:$src1, type0:$src2);
218 let InOperandList = (ins type0:$src1, type0:$src2);
226 let InOperandList = (ins type0:$src1, type0:$src2);
234 let InOperandList = (ins type0:$src1, type0:$src2);
242 let InOperandList = (ins type0:$src1, type0:$src2);
[all …]
/freebsd-12.1/contrib/cortex-strings/src/aarch64/
H A Dstrcmp.S46 #define src2 x1 macro
65 eor tmp1, src1, src2
76 ldr data2, [src2], #8
141 bic src2, src2, #7
145 ldr data2, [src2], #8
161 ldrb data2w, [src2], #1
H A Dmemcmp.S44 #define src2 x1 macro
65 eor tmp1, src1, src2
75 ldr data2, [src2], #8
126 bic src2, src2, #7
131 ldr data2, [src2], #8
156 ldrb data2w, [src2], #1
/freebsd-12.1/contrib/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.td450 let Constraints = "$src2 = $rd" in {
994 def : Pat<(addc GR16:$src, GR16:$src2),
998 def : Pat<(addc GR16:$src, imm:$src2),
1005 def : Pat<(addc GR8:$src, GR8:$src2),
1006 (ADD8rr GR8:$src, GR8:$src2)>;
1009 def : Pat<(addc GR8:$src, imm:$src2),
1010 (ADD8ri GR8:$src, imm:$src2)>;
1016 def : Pat<(subc GR16:$src, GR16:$src2),
1020 def : Pat<(subc GR16:$src, imm:$src2),
1027 def : Pat<(subc GR8:$src, GR8:$src2),
[all …]

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