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/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonDepMapAsm2Intrin.td17 def: Pat<(int_hexagon_S2_vsatwh DoubleRegs:$src1),
53 def: Pat<(int_hexagon_A2_notp DoubleRegs:$src1),
69 def: Pat<(int_hexagon_S2_cl1 IntRegs:$src1),
85 def: Pat<(int_hexagon_A2_abssat IntRegs:$src1),
117 def: Pat<(int_hexagon_C2_not PredRegs:$src1),
1909 def: Pat<(int_hexagon_V6_lo HvxWR:$src1),
1949 def: Pat<(int_hexagon_V6_vsh HvxVR:$src1),
1957 def: Pat<(int_hexagon_V6_vsb HvxVR:$src1),
2017 def: Pat<(int_hexagon_V6_vzh HvxVR:$src1),
2089 def: Pat<(int_hexagon_V6_vzb HvxVR:$src1),
[all …]
H A DHexagonMapAsm2IntrinV65.gen.td17 def: Pat<(int_hexagon_V6_vabsb HvxVR:$src1), (V6_vabsb HvxVR:$src1)>, Requires<[HasV65, UseHVX]>;
18 def: Pat<(int_hexagon_V6_vabsb_128B HvxVR:$src1), (V6_vabsb HvxVR:$src1)>, Requires<[HasV65, UseHVX…
19 def: Pat<(int_hexagon_V6_vabsb_sat HvxVR:$src1), (V6_vabsb_sat HvxVR:$src1)>, Requires<[HasV65, Use…
20 def: Pat<(int_hexagon_V6_vabsb_sat_128B HvxVR:$src1), (V6_vabsb_sat HvxVR:$src1)>, Requires<[HasV65…
29 def: Pat<(int_hexagon_V6_vavgb HvxVR:$src1, HvxVR:$src2), (V6_vavgb HvxVR:$src1, HvxVR:$src2)>, Req…
53 def: Pat<(int_hexagon_V6_vprefixqb HvxQR:$src1), (V6_vprefixqb HvxQR:$src1)>, Requires<[HasV65, Use…
54 def: Pat<(int_hexagon_V6_vprefixqb_128B HvxQR:$src1), (V6_vprefixqb HvxQR:$src1)>, Requires<[HasV65…
55 def: Pat<(int_hexagon_V6_vprefixqh HvxQR:$src1), (V6_vprefixqh HvxQR:$src1)>, Requires<[HasV65, Use…
56 def: Pat<(int_hexagon_V6_vprefixqh_128B HvxQR:$src1), (V6_vprefixqh HvxQR:$src1)>, Requires<[HasV65…
57 def: Pat<(int_hexagon_V6_vprefixqw HvxQR:$src1), (V6_vprefixqw HvxQR:$src1)>, Requires<[HasV65, Use…
[all …]
H A DHexagonMapAsm2IntrinV62.gen.td11 def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
12 (MI HvxVR:$src1, IntRegs:$src2)>;
14 (MI HvxVR:$src1, IntRegs:$src2)>;
26 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2),
27 (MI HvxVR:$src1, HvxVR:$src2)>;
29 (MI HvxVR:$src1, HvxVR:$src2)>;
34 (MI HvxWR:$src1, HvxWR:$src2)>;
36 (MI HvxWR:$src1, HvxWR:$src2)>;
93 def: Pat<(IntID IntRegs:$src1),
94 (MI IntRegs:$src1)>;
[all …]
H A DHexagonIntrinsicsV60.td86 def: Pat<(IntID IntRegs:$src1), (MI IntRegs:$src1)>;
88 (MI IntRegs:$src1)>;
92 def: Pat<(IntID HvxVR:$src1),
93 (MI HvxVR:$src1)>;
96 (MI HvxVR:$src1)>;
100 def: Pat<(IntID HvxWR:$src1),
101 (MI HvxWR:$src1)>;
104 (MI HvxWR:$src1)>;
108 def: Pat<(IntID HvxQR:$src1),
109 (MI HvxQR:$src1)>;
[all …]
H A DHexagonIntrinsics.td136 def : Pat <(int_hexagon_C2_cmplt I32:$src1, I32:$src2),
137 (C2_tfrpr (C2_cmpgt I32:$src2, I32:$src1))>;
281 def : Pat <(v512i1 (bitconvert (v16i32 HvxVR:$src1))),
285 def : Pat <(v512i1 (bitconvert (v32i16 HvxVR:$src1))),
361 def: Pat<(IntID HvxVR:$src1, u3_0ImmPred:$src2),
362 (MI HvxVR:$src1, HvxVR:$src1, u3_0ImmPred:$src2)>,
366 (MI HvxVR:$src1, HvxVR:$src1, u3_0ImmPred:$src2)>,
371 def: Pat<(IntID HvxVR:$src1, u3_64_ImmPred:$src2),
372 (MI HvxVR:$src1, HvxVR:$src1,
377 (MI HvxVR:$src1, HvxVR:$src1, (SUB_128_VAL u3_128_ImmPred:$src2))>,
[all …]
/freebsd-12.1/contrib/sendmail/libsm/
H A Dt-strl.c92 (void) sm_strlcpy(src1[k], "abcdef", sizeof src1);
99 one = sm_strlcpyn(dst1, 10, 3, src1[0], "/", src1[1]);
103 one = sm_strlcpyn(dst1, 5, 3, src1[0], "/", src1[1]);
104 two = sm_snprintf(dst2, 5, "%s/%s", src1[0], src1[1]);
107 one = sm_strlcpyn(dst1, 0, 3, src1[0], "/", src1[1]);
111 one = sm_strlcpyn(dst1, sizeof dst1, 5, src1[0], "/", src1[1], "/", src1[2]);
112 two = sm_snprintf(dst2, sizeof dst2, "%s/%s/%s", src1[0], src1[1], src1[2]);
115 one = sm_strlcpyn(dst1, 15, 5, src1[0], "/", src1[1], "/", src1[2]);
116 two = sm_snprintf(dst2, 15, "%s/%s/%s", src1[0], src1[1], src1[2]);
119 one = sm_strlcpyn(dst1, 20, 5, src1[0], "/", src1[1], "/", src1[2]);
[all …]
H A Db-strcmp.c56 char src1[SIZE], src2[SIZE]; local
87 (void) sm_strlcpy(src1, "1234567890", SIZE);
91 (void) sm_strlcpy(src1, "1234567890", SIZE);
95 (void) sm_strlcpy(src1, "1234567892", SIZE);
100 k, src1, src2);
108 j += strcasecmp(src1, src2);
119 j += sm_strcasecmp(src1, src2);
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86InstrXOP.td175 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
182 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
252 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
260 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
302 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
310 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
318 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
349 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
357 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
364 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[all …]
H A DX86InstrShiftRotate.td521 "rol{b}\t{$src1, $dst|$dst, $src1}",
524 "rol{w}\t{$src1, $dst|$dst, $src1}",
528 "rol{l}\t{$src1, $dst|$dst, $src1}",
532 "rol{q}\t{$src1, $dst|$dst, $src1}",
834 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
839 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
847 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
852 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
938 (SARX32rm addr:$src1,
942 (SARX64rm addr:$src1,
[all …]
H A DX86InstrSSE.td6126 "vptest\t{$src2, $src1|$src1, $src2}",
6130 "vptest\t{$src2, $src1|$src1, $src2}",
6136 "vptest\t{$src2, $src1|$src1, $src2}",
6140 "vptest\t{$src2, $src1|$src1, $src2}",
6148 "ptest\t{$src2, $src1|$src1, $src2}",
6152 "ptest\t{$src2, $src1|$src1, $src2}",
7003 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7175 "vaesimc\t{$src1, $dst|$dst, $src1}",
7181 "vaesimc\t{$src1, $dst|$dst, $src1}",
7187 "aesimc\t{$src1, $dst|$dst, $src1}",
[all …]
H A DX86InstrCompiler.td1236 (TEST8rr GR8:$src1, GR8:$src1)>;
1238 (TEST16rr GR16:$src1, GR16:$src1)>;
1240 (TEST32rr GR32:$src1, GR32:$src1)>;
1242 (TEST64rr GR64:$src1, GR64:$src1)>;
1712 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
1713 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
1714 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
1715 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
2063 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
2064 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
[all …]
H A DX86InstrFMA.td395 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
402 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
409 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
433 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
439 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
470 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
477 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
484 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
497 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
504 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[all …]
H A DX86InstrAVX512.td288 // $src1.
787 "$idx, $src1", "$src1, $idx",
2516 "$src2, $src1", "$src1, $src2",
2525 "$src2, $src1", "$src1, $src2",
4694 "$src2, $src1", "$src1, $src2",
5625 "$src2, $src1", "$src1, $src2",
10492 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
10547 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
10552 (ins _.MemOp:$src1), OpcodeStr, "$src1", "$src1",
11374 "$src1", "$src1",
[all …]
H A DX86InstrArithmetic.td201 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
207 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
213 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
219 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
245 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
258 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
645 mnemonic, "{$src2, $src1|$src1, $src2}", pattern>,
695 mnemonic, "{$src2, $src1|$src1, $src2}", []>,
708 mnemonic, "{$src2, $src1|$src1, $src2}", pattern>,
738 mnemonic, "{$src2, $src1|$src1, $src2}", pattern>,
[all …]
H A DX86InstrVMX.td20 def INVEPT32 : I<0x80, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
21 "invept\t{$src2, $src1|$src1, $src2}", []>, T8PD,
23 def INVEPT64 : I<0x80, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
24 "invept\t{$src2, $src1|$src1, $src2}", []>, T8PD,
28 def INVVPID32 : I<0x81, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
29 "invvpid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
31 def INVVPID64 : I<0x81, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
32 "invvpid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
H A DX86InstrMPX.td31 def 32rm: I<opc, MRMSrcMem, (outs), (ins BNDR:$src1, anymem:$src2),
32 OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
34 def 64rm: I<opc, MRMSrcMem, (outs), (ins BNDR:$src1, anymem:$src2),
35 OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
38 def 32rr: I<opc, MRMSrcReg, (outs), (ins BNDR:$src1, GR32:$src2),
39 OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
41 def 64rr: I<opc, MRMSrcReg, (outs), (ins BNDR:$src1, GR64:$src2),
42 OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
H A DX86InstrMMX.td32 let Constraints = "$src1 = $dst" in {
98 (ins VR64:$src1, VR64:$src2),
103 (ins VR64:$src1, i64mem:$src2),
106 (IntId64 VR64:$src1,
123 [(set VR64:$dst, (IntId VR64:$src1,
394 let Constraints = "$src1 = $dst" in
496 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
502 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
524 let Constraints = "$src1 = $dst" in {
535 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
[all …]
H A DX86InstrCMovSetCC.td19 let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
22 : I<opc, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
25 (X86cmov GR16:$src1, GR16:$src2, CondNode, EFLAGS))]>,
28 : I<opc, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
31 (X86cmov GR32:$src1, GR32:$src2, CondNode, EFLAGS))]>,
34 :RI<opc, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
37 (X86cmov GR64:$src1, GR64:$src2, CondNode, EFLAGS))]>, TB;
43 : I<opc, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
45 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
50 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
[all …]
/freebsd-12.1/contrib/cortex-strings/src/arm/
H A Dstrcmp.S81 #define src1 r0 macro
164 ldrb r2, [src1]
176 orr tmp1, src1, src2
185 eor tmp1, src1, src2
191 and tmp1, src1, #7
192 bic src1, src1, #7
254 ands tmp1, src1, #3
260 ldr data1, [src1], #8
283 bic src1, src1, #3
296 ands tmp1, src1, #3
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DVOP2Instructions.td17 bits<8> src1;
29 bits<8> src1;
42 bits<8> src1;
53 bits<9> src1;
506 (Inst $src0, $src1),
507 (Inst $src1, $src0)
606 (inst $src0, $src1)
611 (inst $src0, $src1)
627 (inst $src1, $src0)
632 (inst $src1, $src0)
[all …]
H A DAMDGPUGISel.td44 (dst_vt (node (src0_vt SReg_32:$src0), (src1_vt SReg_32:$src1))),
45 (inst src0_vt:$src0, src1_vt:$src1)
54 (dst_vt (node (src0_vt (sd_vsrc0 src0_vt:$src0)), (src1_vt VGPR_32:$src1))),
55 (inst src0_vt:$src0, src1_vt:$src1)
64 (dst_vt (node (src1_vt VGPR_32:$src1), (src0_vt (sd_vsrc0 src0_vt:$src0)))),
65 (inst src0_vt:$src0, src1_vt:$src1)
74 (dst_vt (node (src0_vt (sd_vcsrc src0_vt:$src0)), (src1_vt (sd_vcsrc src1_vt:$src1)))),
75 (inst src0_vt:$src0, src1_vt:$src1)
85 (inst src0_vt:$src1, src1_vt:$src0)
95 (src1_vt (VOP3Mods src1_vt:$src1, i32:$src1_modifiers)))),
[all …]
/freebsd-12.1/contrib/llvm/include/llvm/Target/
H A DGenericOpcodes.td178 let InOperandList = (ins type0:$src1, type0:$src2);
518 let InOperandList = (ins type0:$src1);
525 let InOperandList = (ins type0:$src1);
532 let InOperandList = (ins type0:$src1);
539 let InOperandList = (ins type0:$src1);
546 let InOperandList = (ins type0:$src1);
553 let InOperandList = (ins type0:$src1);
562 let InOperandList = (ins type0:$src1);
568 let InOperandList = (ins type0:$src1);
737 let InOperandList = (ins unknown:$src1);
[all …]
/freebsd-12.1/contrib/cortex-strings/src/aarch64/
H A Dstrcmp.S45 #define src1 x0 macro
65 eor tmp1, src1, src2
69 ands tmp1, src1, #7
75 ldr data1, [src1], #8
140 bic src1, src1, #7
143 ldr data1, [src1], #8
160 ldrb data1w, [src1], #1
H A Dmemcmp.S43 #define src1 x0 macro
65 eor tmp1, src1, src2
68 ands tmp1, src1, #7
74 ldr data1, [src1], #8
125 bic src1, src1, #7
129 ldr data1, [src1], #8
155 ldrb data1w, [src1], #1
/freebsd-12.1/contrib/gcc/
H A Dreg-stack.c1238 rtx *src1, *src2; in compare_for_stack_reg() local
1246 if ((! STACK_REG_P (*src1) in compare_for_stack_reg()
1406 rtx *src1 = (rtx *) 0, *src2; in subst_stack_regs_pat() local
1446 src1 = src; in subst_stack_regs_pat()
1459 if (src1 == 0) in subst_stack_regs_pat()
1496 if (STACK_REG_P (*src1)) in subst_stack_regs_pat()
1528 if (STACK_REG_P (*src1)) in subst_stack_regs_pat()
1529 replace_reg (src1, get_hard_regnum (regstack, *src1)); in subst_stack_regs_pat()
1599 int tmp = REGNO (*src1); in subst_stack_regs_pat()
1887 if (STACK_REG_P (*src1)) in subst_stack_regs_pat()
[all …]

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