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/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DSIInstructions.td63 let DisableEncoding = "$src0", Constraints = "$src0 = $vdst" in {
73 } // End DisableEncoding = "$src0", Constraints = "$src0 = $vdst"
173 (ins SSrc_b64:$src0)> {
377 (outs), (ins SSrc_b64:$src0), [(AMDGPUcall i64:$src0)]> {
1128 (i32 (ext i1:$src0)),
1331 (S_NOT_B64 $src0)
1336 (S_NOT_B64 $src0)
1500 (v2i16 (COPY $src0))
1505 (v2f16 (COPY $src0))
1549 (COPY $src0)
[all …]
H A DSOPInstructions.td73 bits<8> src0;
89 "$src0", pattern> {
95 "$src0", pattern> {
124 opName, (outs), (ins SReg_64:$src0), "$src0", pattern> {
308 bits<8> src0;
340 (ops node:$src0),
341 (Op $src0),
347 (Op $src0, $src1),
512 "$src0, $src1"
525 "$src0, $src1"
[all …]
H A DVOP2Instructions.td16 bits<9> src0;
28 bits<9> src0;
506 (Inst $src0, $src1),
507 (Inst $src1, $src0)
605 (op i16:$src0, i16:$src1),
606 (inst $src0, $src1)
611 (inst $src0, $src1)
626 (op i16:$src0, i16:$src1),
627 (inst $src1, $src0)
632 (inst $src1, $src0)
[all …]
H A DAMDGPUInstructions.td139 (ops node:$src0),
140 (op $src0),
145 (ops node:$src0, node:$src1),
146 (op $src0, $src1),
152 (op $src0, $src1, $src2),
188 (ops node:$src0), (srl_oneuse node:$src0, (i32 16))
193 (ops node:$src0), (i16 (trunc (i32 (srl_16 node:$src0))))
616 (fpow f32:$src0, f32:$src1),
648 (dt rc:$src0)
803 (rotr i32:$src0, i32:$src1),
[all …]
H A DAMDGPUGISel.td44 (dst_vt (node (src0_vt SReg_32:$src0), (src1_vt SReg_32:$src1))),
45 (inst src0_vt:$src0, src1_vt:$src1)
54 (dst_vt (node (src0_vt (sd_vsrc0 src0_vt:$src0)), (src1_vt VGPR_32:$src1))),
55 (inst src0_vt:$src0, src1_vt:$src1)
64 (dst_vt (node (src1_vt VGPR_32:$src1), (src0_vt (sd_vsrc0 src0_vt:$src0)))),
65 (inst src0_vt:$src0, src1_vt:$src1)
74 (dst_vt (node (src0_vt (sd_vcsrc src0_vt:$src0)), (src1_vt (sd_vcsrc src1_vt:$src1)))),
75 (inst src0_vt:$src0, src1_vt:$src1)
84 (dst_vt (node (src0_vt (sd_vcsrc src0_vt:$src0)), (src1_vt (sd_vcsrc src1_vt:$src1)))),
85 (inst src0_vt:$src1, src1_vt:$src0)
[all …]
H A DVOP3PInstructions.td31 (ins FP16InputMods:$src0_modifiers, VCSrc_f16:$src0,
81 (mixlo_inst $src0_modifiers, $src0,
95 (v2f16 (mixhi_inst $src0_modifiers, $src0,
108 (v2f16 (mixhi_inst $src0_modifiers, $src0,
203 (ops node:$src0, node:$src1),
230 (ops node:$src0, node:$src1),
237 (add (add_oneuse (AMDGPUmul_u24_oneuse (srl i32:$src0, (i32 16)),
239 (AMDGPUmul_u24_oneuse (and i32:$src0, (i32 65535)),
242 (Inst (i32 8), $src0, (i32 8), $src1, (i32 8), $src2, (i1 0))
248 (AMDGPUmul_i24_oneuse (sext_inreg i32:$src0, i16),
[all …]
H A DEvergreenInstructions.td414 [(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))],
477 let src0 = 0;
535 " "#name#" $last OQAP, $src0$src0_rel $pred_sel",
626 [(truncstorei8_local i32:$src1, i32:$src0)]
629 [(truncstorei16_local i32:$src1, i32:$src0)]
668 [(set i32:$dst, (sextloadi8_local i32:$src0))]
671 [(set i32:$dst, (az_extloadi8_local i32:$src0))]
674 [(set i32:$dst, (sextloadi16_local i32:$src0))]
677 [(set i32:$dst, (az_extloadi16_local i32:$src0))]
690 def : EGOrCaymanPat<(fp_to_sint f32:$src0), (FLT_TO_INT_eg (TRUNC $src0))>;
[all …]
H A DR600Instructions.td405 (ins i32imm:$src0),
406 "INTERP_LOAD $src0 : $dst">;
653 (ins rc:$src0),
654 "FABS $dst, $src0",
660 (ins rc:$src0),
661 "FNEG $dst, $src0",
1049 (ins R600_Reg128:$src0),
1050 "CUBE $dst $src0",
1187 (fdiv f32:$src0, f32:$src1),
1684 (cnd $src0, $src1, $src2)
[all …]
H A DVOP3Instructions.td15 dag src0 = !if(P.HasOMod,
20 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0),
25 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0),
237 let Ins64 = (ins InterpSlot:$src0,
314 // result = src0 * src1 + src2
323 // result = src0 * src1 + src2
500 (op2 (op1 i16:$src0, i16:$src1), i16:$src2),
501 (inst i16:$src0, i16:$src1, i16:$src2, (i1 0))
581 (inst i32:$src0, i32:$src1, i32:$src2)
601 dag ret1 = (P.DstVT (node P.Src0VT:$src0));
[all …]
H A DVOPInstructions.td171 bits<9> src0;
184 let Inst{40-32} = !if(P.HasSrc0, src0, 0);
236 let Inst{49-41} = src0;
242 bits<9> src0;
266 bits<9> src0;
325 bits<8> src0;
361 bits<9> src0; // {src0_sgpr{0}, src0{7-0}}
490 bits<8> src0;
583 (ops node:$src0),
588 (Op $src0),
[all …]
H A DSIInstrInfo.td395 (ops node:$src1, node:$src0),
396 (srl $src0, $src1)
400 (ops node:$src1, node:$src0),
401 (sra $src0, $src1)
405 (ops node:$src1, node:$src0),
406 (shl $src0, $src1)
1263 (ins Src0RC:$src0))
1475 string src0 = ", $src0";
1506 string src0 = !if(!eq(NumSrcArgs, 1), "$src0", "$src0,");
1527 string isrc0 = !if(!eq(NumSrcArgs, 1), "$src0", "$src0,");
[all …]
H A DVOP1Instructions.td16 bits<9> src0;
18 let Inst{8-0} = !if(P.HasSrc0, src0{8-0}, 0);
120 let Asm64 = "$vdst, $src0$clamp$omod";
147 (ins VGPR_32:$src0),
148 "v_readfirstlane_b32 $vdst, $src0",
167 bits<9> src0;
169 let Inst{8-0} = src0;
249 // Restrict src0 to be VGPR
269 let Ins32 = (ins Src0RC32:$vdst, VSrc_b32:$src0);
389 let Ins32 = (ins VGPR_32:$src0, VGPR_32:$src1);
[all …]
H A DAMDGPUInstrInfo.td202 // out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0
205 // out = (src1 > src0) ? 1 : 0
252 // Special case divide FMA with scale and flags (src0 = Quotient,
257 // Special case divide fixup and flags(src0 = Quotient, src1 =
263 // Look Up 2.0 / pi src0 with segment select src1[4:0]
279 // src0: vec4(src, 0, 0, mask)
381 // i32 or f32 src0
H A DSIPeepholeSDWA.cpp339 if (TII->getNamedOperand(*MI, AMDGPU::OpName::src0) == SrcOp) { in getSrcMods()
374 MachineOperand *Src = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in convertToSDWA()
564 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand()
605 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand()
674 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand()
691 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand()
752 OrOther = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand()
923 NewMI.add(*TII->getNamedOperand(MI, AMDGPU::OpName::src0)); in pseudoOpConvertToVOP2()
929 NewInst.add(*TII->getNamedOperand(MISucc, AMDGPU::OpName::src0)); in pseudoOpConvertToVOP2()
1018 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in convertToSDWA()
[all …]
H A DCaymanInstructions.td24 [(set i32:$dst, (AMDGPUmad_i24 i32:$src0, i32:$src1, i32:$src2))], VecALU
27 [(set i32:$dst, (AMDGPUmul_i24 i32:$src0, i32:$src1))], VecALU
61 (AMDGPUurecip i32:$src0),
62 (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg $src0)),
H A DVOPCInstructions.td15 bits<9> src0;
18 let Inst{8-0} = src0;
57 let Asm32 = "vcc, $src0, $src1";
131 (inst p.DstRC:$sdst, p.Src0RC32:$src0),
134 (inst p.DstRC:$sdst, p.Src0RC32:$src0, p.Src1RC32:$src1),
140 (inst p.Src0RC32:$src0, p.Src1RC32:$src1),
539 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
612 (AMDGPUsetcc vt:$src0, vt:$src1, cond),
613 (inst $src0, $src1)
650 (i64 (AMDGPUsetcc (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)),
[all …]
H A DSIOptimizeExecMaskingPreRA.cpp88 Op = TII.getNamedOperand(MI, AMDGPU::OpName::src0); in getOrNonExecReg()
163 MachineOperand *Op1 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src0); in optimizeVcndVcmpPair()
175 Op1 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src0); in optimizeVcndVcmpPair()
H A DGCNDPPCombine.cpp160 TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0)->getReg()); in createDPPInst()
194 auto *Src0 = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0); in createDPPInst()
391 if (&Use == TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0)) { in combineDPPMov()
H A DR600ExpandSpecialInstrs.cpp160 TII->getOperandIdx(Opcode, R600::OpName::src0)) in runOnMachineFunction()
212 TII->getOperandIdx(MI, R600::OpName::src0)).getReg(); in runOnMachineFunction()
/freebsd-12.1/sys/libkern/
H A Dbcopy.c72 memcpy(void *dst0, const void *src0, size_t length) in memcpy() argument
79 src = src0; in memcpy()
152 (bcopy)(const void *src0, void *dst0, size_t length)
155 memcpy(dst0, src0, length);
/freebsd-12.1/crypto/openssl/crypto/ec/asm/
H A Decp_nistz256-x86_64.pl3050 my ($a,$b,$src0) = @_;
3053 " mov $b, $src0
3063 my ($a,$src0) = @_;
3066 " mov 8*0+$a, $src0
3217 $src0 = "%rax";
3235 $src0 = "%rdx";
3413 mov $M(%rsp), $src0
3468 $src0 = "%rax";
3486 $src0 = "%rdx";
3858 $src0 = "%rax";
[all …]
/freebsd-12.1/lib/libc/string/
H A Dbcopy.c66 (void *dst0, const void *src0, size_t length) in memcpy() argument
71 bcopy(const void *src0, void *dst0, size_t length) in memcpy()
75 const char *src = src0; in memcpy()
/freebsd-12.1/contrib/llvm/lib/Target/NVPTX/
H A DNVPTXIntrinsics.td360 [(set target_regclass:$dst, (IntOP src_regclass:$src0))]>;
367 (ins s0_regclass:$src0, s1_regclass:$src1),
423 def INT_NVVM_MUL_RN_F : F_MATH_2<"mul.rn.f32 \t$dst, $src0, $src1;",
427 def INT_NVVM_MUL_RZ_F : F_MATH_2<"mul.rz.f32 \t$dst, $src0, $src1;",
431 def INT_NVVM_MUL_RM_F : F_MATH_2<"mul.rm.f32 \t$dst, $src0, $src1;",
632 def INT_NVVM_RCP_RN_F : F_MATH_1<"rcp.rn.f32 \t$dst, $src0;",
636 def INT_NVVM_RCP_RZ_F : F_MATH_1<"rcp.rz.f32 \t$dst, $src0;",
640 def INT_NVVM_RCP_RM_F : F_MATH_1<"rcp.rm.f32 \t$dst, $src0;",
644 def INT_NVVM_RCP_RP_F : F_MATH_1<"rcp.rp.f32 \t$dst, $src0;",
860 "mov.b64 \t{$dst, %temp}, $src0;\n\t",
[all …]
/freebsd-12.1/sys/netipsec/
H A Dkey.c1950 struct sadb_address *src0, *dst0; in key_spdadd() local
2024 src0 + 1, in key_spdadd()
2171 struct sadb_address *src0, *dst0; in key_spddelete() local
2224 src0 + 1, in key_spddelete()
4857 struct sadb_address *src0, *dst0; in key_getspi() local
5342 struct sadb_address *src0, *dst0; in key_update() local
5568 struct sadb_address *src0, *dst0; in key_add() local
5998 struct sadb_address *src0, *dst0; in key_delete() local
6217 struct sadb_address *src0, *dst0; in key_get() local
6987 struct sadb_address *src0, *dst0; in key_acquire2() local
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86InstrAVX512.td1471 VR512:$src0),
1479 VR512:$src0),
1488 VR512:$src0),
1496 VR512:$src0),
1524 VR256X:$src0),
1532 VR256X:$src0),
1573 VR256X:$src0),
1606 VR512:$src0),
1614 VR512:$src0),
1623 VR512:$src0),
[all …]

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