| /freebsd-12.1/contrib/llvm/lib/CodeGen/ |
| H A D | ImplicitNullChecks.cpp | 286 if (TRI->regsOverlap(RegA, RegB) && (MOA.isDef() || MOB.isDef())) in canReorder()
440 TRI->regsOverlap(DependenceMO.getReg(), PointerReg)) && in canHoistInst()
599 TRI->regsOverlap(MO.getReg(), PointerReg); in analyzeBlockForNullChecks()
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| H A D | ProcessImplicitDefs.cpp | 106 !TRI->regsOverlap(Reg, UserReg)) in processImplicitDef()
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| H A D | MachineCopyPropagation.cpp | 362 MIUse.isUse() && TRI->regsOverlap(Use.getReg(), MIUse.getReg())) in hasImplicitOverlap()
458 if (MI->isCopy() && !TRI->regsOverlap(MI->getOperand(0).getReg(), in CopyPropagateBlock()
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| H A D | CriticalAntiDepBreaker.cpp | 425 if (TRI->regsOverlap(NewReg, *it)) { in findSuitableFreeRegister()
618 if (MO.isUse() && TRI->regsOverlap(AntiDepReg, Reg)) { in BreakAntiDependencies()
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| H A D | MachineInstrBundle.cpp | 337 if (!TRI->regsOverlap(MOReg, Reg)) in analyzePhysReg()
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| H A D | MachineInstr.cpp | 937 if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg))) in findRegisterUseOperandIdx()
993 Found = TRI->regsOverlap(MOReg, Reg); in findRegisterDefOperandIdx()
1832 if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg) in clearRegisterKills()
1937 [&](unsigned Use) { return TRI.regsOverlap(Use, Reg); })) in setPhysRegsDeadExcept()
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| H A D | RegAllocPBQP.cpp | 420 if (TRI.regsOverlap(PRegN, PRegM)) { in createInterferenceEdge()
573 if (TRI.regsOverlap(reg, CSR[i])) in isACalleeSavedRegister()
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| H A D | VirtRegMap.cpp | 427 if (TRI->regsOverlap(Dst->getOperand(0).getReg(), in expandCopyBundle()
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| H A D | MachineBasicBlock.cpp | 1405 if (TRI->regsOverlap(LI.PhysReg, Reg)) in computeRegisterLiveness()
1460 if (TRI->regsOverlap(LI.PhysReg, Reg)) in computeRegisterLiveness()
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| H A D | MachineCSE.cpp | 220 if (!TRI->regsOverlap(MO.getReg(), Reg)) in isPhysDefTriviallyDead()
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| H A D | TwoAddressInstructionPass.cpp | 568 return TRI->regsOverlap(RegA, RegB); in regsAreCompatible()
575 if (TRI->regsOverlap(R, Reg)) in regOverlapsSet()
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| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86CallFrameOptimization.cpp | 335 if (RegInfo.regsOverlap(Reg, RegInfo.getStackRegister())) in classifyInstruction()
339 if (RegInfo.regsOverlap(Reg, U)) in classifyInstruction()
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| H A D | X86FixupBWInsts.cpp | 260 TRI->regsOverlap(SuperDestReg, MO.getReg())) in getSuperRegDestIfDead()
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| H A D | X86FrameLowering.cpp | 1972 if (TRI->regsOverlap(CSI[i].getReg(),FPReg)) { in assignCalleeSavedSpillSlots()
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64PBQPRegAlloc.cpp | 197 if (livesOverlap && TRI->regsOverlap(pRd, pRa)) in addIntraChainConstraint()
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| H A D | AArch64AsmPrinter.cpp | 344 assert(RI->regsOverlap(RegToPrint, Reg)); in printAsmRegInClass()
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| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 423 bool regsOverlap(unsigned regA, unsigned regB) const { in regsOverlap() function
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMLoadStoreOptimizer.cpp | 1704 if (isLd && TRI->regsOverlap(EvenReg, BaseReg)) { in FixInvalidRegPairOp()
1705 assert(!TRI->regsOverlap(OddReg, BaseReg)); in FixInvalidRegPairOp()
1786 if (TRI->regsOverlap(Reg, E.MI->getOperand(0).getReg())) { in LoadStoreMultipleOpti()
2093 if (MO.isDef() && TRI->regsOverlap(Reg, Base)) in IsSafeAndProfitableToMove()
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| H A D | ARMBaseInstrInfo.cpp | 912 if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) { in copyPhysReg()
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | GCNHazardRecognizer.cpp | 571 TRI->regsOverlap(MI->getOperand(DataIdx).getReg(), Reg); in checkVALUHazardsHelper()
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| H A D | SIShrinkInstructions.cpp | 302 if (TRI.regsOverlap(Reg, MO.getReg())) in instAccessReg()
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| H A D | SIISelLowering.cpp | 2781 Subtarget->getRegisterInfo()->regsOverlap(Reg, AMDGPU::FLAT_SCR)) { in getRegisterByName()
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| /freebsd-12.1/contrib/llvm/lib/Target/SystemZ/ |
| H A D | SystemZElimCompare.cpp | 154 if (TRI->regsOverlap(MOReg, Reg)) { in getRegReferences()
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGRRList.cpp | 2846 if (TRI->regsOverlap(*ImpDef, SuccPred.getReg()) && in canClobberReachingPhysRegUse()
2885 if (TRI->regsOverlap(Reg, SUReg)) in canClobberPhysRegDefs()
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