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Searched refs:regclasses (Results 1 – 11 of 11) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp60 for (const TargetRegisterClass *RC : TRI->regclasses()) in ResourcePriorityQueue()
359 for (const TargetRegisterClass *RC : TRI->regclasses()) in regPressureDelta()
363 for (const TargetRegisterClass *RC : TRI->regclasses()) { in regPressureDelta()
H A DScheduleDAGRRList.cpp1750 for (const TargetRegisterClass *RC : TRI->regclasses()) in RegReductionPQBase()
2056 for (const TargetRegisterClass *RC : TRI->regclasses()) { in dumpRegPressure()
H A DTargetLowering.cpp3265 for (const TargetRegisterClass *RC : RI->regclasses()) { in getRegForInlineAsmConstraint()
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DRegUsageInfoCollector.cpp169 for (const TargetRegisterClass *RC : TRI.regclasses()) { in computeCalleeSavedRegs()
H A DTargetRegisterInfo.cpp198 for (const TargetRegisterClass* RC : regclasses()) { in getMinimalPhysRegClass()
227 for (const TargetRegisterClass *C : regclasses()) in getAllocatableSet()
H A DRegisterClassInfo.cpp171 for (const TargetRegisterClass *C : TRI->regclasses()) { in computePSetLimit()
/freebsd-12.1/contrib/llvm/include/llvm/MC/
H A DMCRegisterInfo.h423 iterator_range<regclass_iterator> regclasses() const { in regclasses() function
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DRDFRegisters.cpp34 for (const TargetRegisterClass *RC : TRI.regclasses()) { in PhysicalRegisterInfo()
H A DHexagonBlockRanges.cpp225 for (const TargetRegisterClass *RC : TRI.regclasses()) { in HexagonBlockRanges()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h686 iterator_range<regclass_iterator> regclasses() const { in regclasses() function
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkorDetails.td582 // FIXME: This could be better modeled by looking at the regclasses of the operands.