Home
last modified time | relevance | path

Searched refs:rdev (Results 1 – 25 of 112) sorted by relevance

12345

/freebsd-12.1/sys/dev/drm2/radeon/
H A Dradeon_pm.c131 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx; in radeon_pm_update_profile()
133 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx; in radeon_pm_update_profile()
156 rdev->irq.vblank_queue, rdev->pm.vblank_sync, in radeon_sync_with_vblank()
519 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev); in radeon_hwmon_init()
567 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, in radeon_pm_resume()
581 rdev->pm.current_sclk = rdev->pm.default_sclk; in radeon_pm_resume()
582 rdev->pm.current_mclk = rdev->pm.default_mclk; in radeon_pm_resume()
608 rdev->pm.default_sclk = rdev->clock.default_sclk; in radeon_pm_init()
609 rdev->pm.default_mclk = rdev->clock.default_mclk; in radeon_pm_init()
610 rdev->pm.current_sclk = rdev->clock.default_sclk; in radeon_pm_init()
[all …]
H A Dradeon_asic.h66 int r100_init(struct radeon_device *rdev);
67 void r100_fini(struct radeon_device *rdev);
68 int r100_suspend(struct radeon_device *rdev);
69 int r100_resume(struct radeon_device *rdev);
77 int r100_irq_set(struct radeon_device *rdev);
251 int rs690_init(struct radeon_device *rdev);
272 int rv515_init(struct radeon_device *rdev);
292 int r520_init(struct radeon_device *rdev);
299 int r600_init(struct radeon_device *rdev);
507 int si_init(struct radeon_device *rdev);
[all …]
H A Dr420.c160 rdev->num_gb_pipes, rdev->num_z_pipes); in r420_pipes_init()
212 radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch); in r420_cp_errata_init()
231 radeon_scratch_free(rdev, rdev->config.r300.resync_scratch); in r420_cp_errata_fini()
270 r100_irq_set(rdev); in r420_startup()
340 r100_cp_fini(rdev); in r420_fini()
341 radeon_wb_fini(rdev); in r420_fini()
358 rdev->bios = NULL; in r420_fini()
390 dev_warn(rdev->dev, in r420_init()
409 r300_mc_init(rdev); in r420_init()
410 r420_debugfs(rdev); in r420_init()
[all …]
H A Dradeon_device.c550 rdev->dummy_page.dmah = drm_pci_alloc(rdev->ddev, in radeon_dummy_page_init()
569 drm_pci_free(rdev->ddev, rdev->dummy_page.dmah); in radeon_dummy_page_fini()
598 r = rdev->pll_rreg(rdev, reg); in cail_pll_read()
615 rdev->pll_wreg(rdev, reg, val); in cail_pll_write()
632 r = rdev->mc_rreg(rdev, reg); in cail_mc_read()
649 rdev->mc_wreg(rdev, reg, val); in cail_mc_write()
1105 rdev->rmmio_base = rman_get_start(rdev->rmmio); in radeon_device_init()
1106 rdev->rmmio_size = rman_get_size(rdev->rmmio); in radeon_device_init()
1179 rdev->mc.agp_base + rdev->mc.gtt_size, in radeon_device_init()
1231 rdev->mc.agp_base + rdev->mc.gtt_size); in radeon_device_fini()
[all …]
H A Dr520.c85 r420_pipes_init(rdev); in r520_gpu_init()
131 radeon_vram_location(rdev, &rdev->mc, 0); in r520_mc_init()
134 radeon_gtt_location(rdev, &rdev->mc); in r520_mc_init()
176 r520_mc_program(rdev); in r520_startup()
180 r520_gpu_init(rdev); in r520_startup()
201 rs600_irq_set(rdev); in r520_startup()
275 dev_warn(rdev->dev, in r520_init()
284 if (!radeon_card_posted(rdev) && rdev->bios) { in r520_init()
298 r520_mc_init(rdev); in r520_init()
299 rv515_debugfs(rdev); in r520_init()
[all …]
H A Dradeon_irq_kms.c113 radeon_irq_set(rdev); in radeon_driver_irq_preinstall_kms()
146 if (rdev == NULL) { in radeon_driver_irq_uninstall_kms()
160 radeon_irq_set(rdev); in radeon_driver_irq_uninstall_kms()
248 TASK_INIT(&rdev->hotplug_work, 0, radeon_hotplug_work_func, rdev); in radeon_irq_kms_init()
249 TASK_INIT(&rdev->audio_work, 0, r600_audio_update_hdmi, rdev); in radeon_irq_kms_init()
252 r = drm_vblank_init(rdev->ddev, rdev->num_crtc); in radeon_irq_kms_init()
292 taskqueue_drain(rdev->tq, &rdev->hotplug_work); in radeon_irq_kms_fini()
412 radeon_irq_set(rdev); in radeon_irq_kms_enable_afmt()
434 radeon_irq_set(rdev); in radeon_irq_kms_disable_afmt()
457 radeon_irq_set(rdev); in radeon_irq_kms_enable_hpd()
[all …]
H A Dr600.c1059 if (rdev->mc.vram_start < rdev->mc.gtt_start) { in r600_mc_program()
1160 radeon_vram_location(rdev, &rdev->mc, base); in r600_vram_gtt_location()
1204 rdev->mc.visible_vram_size = rdev->mc.aper_size; in r600_mc_init()
1205 r600_vram_gtt_location(rdev, &rdev->mc); in r600_mc_init()
2163 if (!rdev->me_fw || !rdev->pfp_fw) in r600_cp_load_microcode()
2790 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { in r600_startup()
3022 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { in r600_init()
3257 rdev->ih.ptr_mask = rdev->ih.ring_size - 1; in r600_ih_ring_init()
3268 r = radeon_bo_create(rdev, rdev->ih.ring_size, in r600_ih_ring_alloc()
3890 if (!rdev->ih.enabled || rdev->shutdown) in r600_irq_process()
[all …]
H A Drs400.c82 if (rdev->gart.ptr) { in rs400_gart_init()
105 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; in rs400_gart_init()
145 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { in rs400_gart_enable()
154 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { in rs400_gart_enable()
178 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { in rs400_gart_enable()
262 rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev); in rs400_mc_init()
268 radeon_vram_location(rdev, &rdev->mc, base); in rs400_mc_init()
269 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1; in rs400_mc_init()
270 radeon_gtt_location(rdev, &rdev->mc); in rs400_mc_init()
305 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { in rs400_debugfs_gart_info()
[all …]
H A Drv770.c269 if (rdev->mc.vram_start < rdev->mc.gtt_start) { in rv770_mc_program()
319 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); in r700_cp_stop()
330 if (!rdev->me_fw || !rdev->pfp_fw) in rv770_cp_load_microcode()
333 r700_cp_stop(rdev); in rv770_cp_load_microcode()
842 radeon_vram_location(rdev, &rdev->mc, 0); in r700_vram_gtt_location()
881 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); in rv770_mc_init()
882 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); in rv770_mc_init()
886 rdev->mc.visible_vram_size = rdev->mc.aper_size; in rv770_mc_init()
887 r700_vram_gtt_location(rdev, &rdev->mc); in rv770_mc_init()
975 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { in rv770_startup()
[all …]
H A Drs600.c490 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; in rs600_gart_init()
758 taskqueue_enqueue(rdev->tq, &rdev->hotplug_work); in rs600_irq_process()
760 taskqueue_enqueue(rdev->tq, &rdev->audio_work); in rs600_irq_process()
810 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); in rs600_mc_init()
811 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); in rs600_mc_init()
815 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; in rs600_mc_init()
816 rdev->mc.visible_vram_size = rdev->mc.aper_size; in rs600_mc_init()
820 radeon_vram_location(rdev, &rdev->mc, base); in rs600_mc_init()
822 radeon_gtt_location(rdev, &rdev->mc); in rs600_mc_init()
998 r100_cp_fini(rdev); in rs600_fini()
[all …]
H A Dni.c222 if (!rdev->mc_fw) in ni_mc_load_microcode()
987 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); in cayman_cp_enable()
999 if (!rdev->me_fw || !rdev->pfp_fw) in cayman_cp_load_microcode()
1262 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); in cayman_dma_stop()
1364 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); in cayman_dma_resume()
1379 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]); in cayman_dma_fini()
1380 radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]); in cayman_dma_fini()
1566 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { in cayman_startup()
1574 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) { in cayman_startup()
1843 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) { in cayman_init()
[all …]
H A Dradeon.h1819 #define radeon_init(rdev) (rdev)->asic->init((rdev)) argument
1820 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) argument
1821 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) argument
1822 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) argument
1828 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) argument
1838 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) argument
1861 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) argument
1862 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) argument
1865 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) argument
1866 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) argument
[all …]
H A Devergreen.c1547 if (rdev->mc.vram_start < rdev->mc.gtt_start) { in evergreen_mc_program()
1643 if (!rdev->me_fw || !rdev->pfp_fw) in evergreen_cp_load_microcode()
2415 rdev->mc.visible_vram_size = rdev->mc.aper_size; in evergreen_mc_init()
2416 r700_vram_gtt_location(rdev, &rdev->mc); in evergreen_mc_init()
3010 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; in evergreen_get_ih_wptr()
3027 if (!rdev->ih.enabled || rdev->shutdown) in evergreen_irq_process()
3363 taskqueue_enqueue(rdev->tq, &rdev->hotplug_work); in evergreen_irq_process()
3365 taskqueue_enqueue(rdev->tq, &rdev->audio_work); in evergreen_irq_process()
3524 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) { in evergreen_startup()
3537 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { in evergreen_startup()
[all …]
H A Dradeon_fence.c114 (*fence)->rdev = rdev; in radeon_fence_emit()
371 if (radeon_ring_is_lockup(rdev, ring, &rdev->ring[ring])) { in radeon_fence_wait_seq()
525 rdev, target_seq); in radeon_fence_wait_any_seq()
566 if (radeon_ring_is_lockup(rdev, ring, &rdev->ring[ring])) { in radeon_fence_wait_any_seq()
821 radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg); in radeon_fence_driver_start_ring()
822 if (rdev->wb.use_event || !radeon_ring_supports_scratch_reg(rdev, &rdev->ring[ring])) { in radeon_fence_driver_start_ring()
826 r = radeon_scratch_get(rdev, &rdev->fence_drv[ring].scratch_reg); in radeon_fence_driver_start_ring()
835 rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4]; in radeon_fence_driver_start_ring()
836 rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr + index; in radeon_fence_driver_start_ring()
918 radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg); in radeon_fence_driver_fini()
[all …]
H A Dradeon_gart.c74 dmah = drm_pci_alloc(rdev->ddev, rdev->gart.table_size, in radeon_gart_table_ram_alloc()
89 memset((void *)rdev->gart.ptr, 0, rdev->gart.table_size); in radeon_gart_table_ram_alloc()
114 drm_pci_free(rdev->ddev, rdev->gart.dmah); in radeon_gart_table_ram_free()
135 r = radeon_bo_create(rdev, rdev->gart.table_size, in radeon_gart_table_vram_alloc()
169 r = radeon_bo_kmap(rdev->gart.robj, &rdev->gart.ptr); in radeon_gart_table_vram_pin()
249 rdev->gart.pages_addr[p] = rdev->dummy_page.addr; in radeon_gart_unbind()
358 rdev->gart.num_cpu_pages = rdev->mc.gtt_size / PAGE_SIZE; in radeon_gart_init()
361 rdev->gart.num_cpu_pages, rdev->gart.num_gpu_pages); in radeon_gart_init()
378 rdev->gart.pages_addr[i] = rdev->dummy_page.addr; in radeon_gart_init()
392 if (rdev->gart.pages && rdev->gart.pages_addr && rdev->gart.ready) { in radeon_gart_fini()
[all …]
H A Drs690.c160 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; in rs690_mc_init()
162 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); in rs690_mc_init()
163 rdev->mc.visible_vram_size = rdev->mc.aper_size; in rs690_mc_init()
168 radeon_vram_location(rdev, &rdev->mc, base); in rs690_mc_init()
169 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1; in rs690_mc_init()
170 radeon_gtt_location(rdev, &rdev->mc); in rs690_mc_init()
306 rdev->pm.max_bandwidth = rdev->pm.core_bandwidth; in rs690_crtc_bandwidth_compute()
310 rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth; in rs690_crtc_bandwidth_compute()
319 rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth; in rs690_crtc_bandwidth_compute()
322 rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth; in rs690_crtc_bandwidth_compute()
[all …]
H A Dsi.c1721 si_setup_rb(rdev, rdev->config.si.max_shader_engines, in si_gpu_init()
1725 si_setup_spi(rdev, rdev->config.si.max_shader_engines, in si_gpu_init()
1906 if (!rdev->me_fw || !rdev->pfp_fw) in si_cp_load_microcode()
2410 si_vram_location(rdev, &rdev->mc, 0); in si_vram_gtt_location()
2468 rdev->mc.visible_vram_size = rdev->mc.aper_size; in si_mc_init()
2469 si_vram_gtt_location(rdev, &rdev->mc); in si_mc_init()
3709 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; in si_get_ih_wptr()
3735 if (!rdev->ih.enabled || rdev->shutdown) in si_irq_process()
4021 taskqueue_enqueue(rdev->tq, &rdev->hotplug_work); in si_irq_process()
4116 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw || in si_startup()
[all …]
H A Dr300.c99 if (rdev->gart.robj) { in rv370_pcie_gart_init()
110 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; in rv370_pcie_gart_init()
332 if ((rdev->family == CHIP_R300 && rdev->ddev->pci_device != 0x4144) || in r300_gpu_init()
333 (rdev->family == CHIP_R350 && rdev->ddev->pci_device != 0x4148)) { in r300_gpu_init()
380 rdev->num_gb_pipes, rdev->num_z_pipes); in r300_gpu_init()
462 radeon_vram_location(rdev, &rdev->mc, base); in r300_mc_init()
465 radeon_gtt_location(rdev, &rdev->mc); in r300_mc_init()
1348 if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380)) in r300_clock_startup()
1396 r100_irq_set(rdev); in r300_startup()
1474 rdev->bios = NULL; in r300_fini()
[all …]
H A Dradeon_kms.c53 if (rdev == NULL) in radeon_driver_unload_kms()
55 if (rdev->rmmio == NULL) in radeon_driver_unload_kms()
57 radeon_acpi_fini(rdev); in radeon_driver_unload_kms()
58 radeon_modeset_fini(rdev); in radeon_driver_unload_kms()
59 radeon_device_fini(rdev); in radeon_driver_unload_kms()
62 free(rdev, DRM_MEM_DRIVER); in radeon_driver_unload_kms()
82 struct radeon_device *rdev; in radeon_driver_load_kms() local
86 if (rdev == NULL) { in radeon_driver_load_kms()
232 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) in radeon_info_ioctl()
527 rdev->cmask_filp = NULL; in radeon_driver_preclose_kms()
[all …]
H A Dr600_blit_kms.c94 if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) { in set_render_target()
518 if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) in r600_blit_init()
571 rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset); in r600_blit_init()
597 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); in r600_blit_init()
684 r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, vb, in r600_blit_prepare_copy()
714 rdev->r600_blit.primitives.set_default_state(rdev); in r600_blit_prepare_copy()
715 rdev->r600_blit.primitives.set_shaders(rdev); in r600_blit_prepare_copy()
774 rdev->r600_blit.primitives.set_tex_resource(rdev, FMT_8_8_8_8, in r600_kms_blit_copy()
778 rdev->r600_blit.primitives.set_scissors(rdev, 0, 0, w, h); in r600_kms_blit_copy()
780 rdev->r600_blit.primitives.draw_auto(rdev); in r600_kms_blit_copy()
[all …]
H A Dr100.c297 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r100_pm_get_dynpm_state()
299 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r100_pm_get_dynpm_state()
661 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; in r100_pci_gart_init()
820 taskqueue_enqueue(rdev->tq, &rdev->hotplug_work); in r100_irq_process()
2893 if (rdev->mc.visible_vram_size > rdev->mc.aper_size) in r100_vram_init_sizes()
2894 rdev->mc.visible_vram_size = rdev->mc.aper_size; in r100_vram_init_sizes()
2902 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; in r100_vram_init_sizes()
2921 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; in r100_vram_init_sizes()
2948 radeon_vram_location(rdev, &rdev->mc, base); in r100_mc_init()
2951 radeon_gtt_location(rdev, &rdev->mc); in r100_mc_init()
[all …]
H A Dradeon_ring.c70 r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &ib->sa_bo, size, 256, true); in radeon_ib_get()
207 if (rdev->ib_pool_ready) { in radeon_ib_pool_init()
210 r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo, in radeon_ib_pool_init()
217 r = radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo); in radeon_ib_pool_init()
222 rdev->ib_pool_ready = true; in radeon_ib_pool_init()
241 if (rdev->ib_pool_ready) { in radeon_ib_pool_fini()
242 radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo); in radeon_ib_pool_fini()
243 radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo); in radeon_ib_pool_fini()
361 if (rdev->wb.enabled) in radeon_ring_free_size()
608 else if (rdev->wb.enabled) in radeon_ring_backup()
[all …]
H A Drv515.c207 radeon_vram_location(rdev, &rdev->mc, 0); in rv515_mc_init()
210 radeon_gtt_location(rdev, &rdev->mc); in rv515_mc_init()
539 rs600_irq_set(rdev); in rv515_startup()
605 r100_cp_fini(rdev); in rv515_fini()
616 rdev->bios = NULL; in rv515_fini()
645 dev_warn(rdev->dev, in rv515_init()
663 rv515_mc_init(rdev); in rv515_init()
664 rv515_debugfs(rdev); in rv515_init()
686 r100_cp_fini(rdev); in rv515_init()
1099 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0); in rv515_bandwidth_avivo_update()
[all …]
/freebsd-12.1/sys/dev/cxgbe/iw_cxgbe/
H A Dresource.c57 i < rdev->adap->vres.qp.start + rdev->adap->vres.qp.size; i++) in c4iw_init_qid_table()
124 rdev->stats.qid.cur += rdev->qpmask + 1; in c4iw_get_cqid()
155 if (rdev->stats.qid.cur > rdev->stats.qid.max) in c4iw_get_cqid()
156 rdev->stats.qid.max = rdev->stats.qid.cur; in c4iw_get_cqid()
194 rdev->stats.qid.cur += rdev->qpmask + 1; in c4iw_get_qpid()
225 if (rdev->stats.qid.cur > rdev->stats.qid.max) in c4iw_get_qpid()
226 rdev->stats.qid.max = rdev->stats.qid.cur; in c4iw_get_qpid()
268 if (rdev->stats.pbl.cur > rdev->stats.pbl.max) in c4iw_pblpool_alloc()
269 rdev->stats.pbl.max = rdev->stats.pbl.cur; in c4iw_pblpool_alloc()
322 if (rdev->stats.rqt.cur > rdev->stats.rqt.max) in c4iw_rqtpool_alloc()
[all …]
H A Ddevice.c65 rdev->stats.qid.cur -= rdev->qpmask + 1; in c4iw_release_dev_ucontext()
98 c4iw_init_dev_ucontext(rdev, &rdev->uctx); in c4iw_rdev_open()
137 rc = c4iw_init_resource(rdev, c4iw_num_stags(rdev), T4_MAX_NUM_PD); in c4iw_rdev_open()
154 if (!rdev->status_page) { in c4iw_rdev_open()
168 rdev->status_page->wc_supported = rdev->adap->iwt.wc_en; in c4iw_rdev_open()
171 if (!rdev->free_workq) { in c4iw_rdev_open()
218 iwsc->rdev.adap = sc; in c4iw_alloc()
234 iwsc->rdev.hw_queue.t4_stat_len = iwsc->rdev.adap->params.sge.spg_len; in c4iw_alloc()
239 iwsc->rdev.bar2_kva = (void __iomem *)((u64)iwsc->rdev.adap->udbs_base); in c4iw_alloc()
240 iwsc->rdev.bar2_pa = vtophys(iwsc->rdev.adap->udbs_base); in c4iw_alloc()
[all …]

12345