| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPatternsV65.td | 11 let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1, mayStore = 1 in 20 let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1, mayStore = 1 in 29 let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1, mayStore = 1 in 42 let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1, mayStore = 1 in 51 let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1, mayStore = 1 in 60 let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1, mayStore = 1 in
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| H A D | HexagonOptAddrMode.cpp | 129 if ((!MID.mayStore() && !MID.mayLoad()) || HII->isPredicated(MI)) in INITIALIZE_PASS_DEPENDENCY() 132 if (MID.mayStore()) { in INITIALIZE_PASS_DEPENDENCY() 195 if ((!UseMID.mayLoad() && !UseMID.mayStore()) || in canRemoveAddasl() 201 if (UseMID.mayStore() && UseMI.getOperand(2).isReg() && in canRemoveAddasl() 358 if ((!MID.mayLoad() && !MID.mayStore()) || in processAddUses() 445 if ((MID.mayLoad() || MID.mayStore())) { in analyzeUses() 648 } else if (UseMID.mayStore()) { in changeAddAsl() 676 else if (MID.mayStore()) in xformUseMI()
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| H A D | HexagonVLIWPacketizer.cpp | 357 if (HII->isHVXVec(MI) && MI.mayStore()) in isNewifiable() 590 if (MI.getDesc().mayStore()) { in getPostIncrementOperand() 666 if (PacketSU->getInstr()->mayStore()) in canPromoteToNewValueStore() 1109 if (HII.isNewValueStore(MI) && MJ.mayStore()) in cannotCoexistAsymm() 1288 bool StoreI = I.mayStore(), StoreJ = J.mayStore(); in hasDualStoreDependence() 1373 if (PI->getOpcode() == Hexagon::S2_allocframe || PI->mayStore() || in isLegalToPacketizeTogether() 1515 bool LoadJ = J.mayLoad(), StoreJ = J.mayStore(); in isLegalToPacketizeTogether() 1516 bool LoadI = I.mayLoad(), StoreI = I.mayStore(); in isLegalToPacketizeTogether() 1680 if (MJ->mayStore() && !HII->isNewValueStore(*MJ)) in foundLSInPacket()
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| H A D | HexagonVectorPrint.cpp | 117 if (MI.mayStore() && MI.getNumOperands() >= 3 && MI.getOperand(2).isReg()) { in getInstrVecReg() 123 if (MI.mayStore() && MI.getNumOperands() >= 4 && MI.getOperand(3).isReg()) { in getInstrVecReg()
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| H A D | HexagonDepInstrInfo.td | 11205 let mayStore = 1; 11232 let mayStore = 1; 11259 let mayStore = 1; 11286 let mayStore = 1; 11313 let mayStore = 1; 11340 let mayStore = 1; 11367 let mayStore = 1; 11394 let mayStore = 1; 11421 let mayStore = 1; 11448 let mayStore = 1; [all …]
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| H A D | HexagonSubtarget.cpp | 149 bool IsStoreMI1 = MI1.mayStore(); in apply() 159 if ((IsStoreMI1 && MI2.mayStore()) || (IsLoadMI1 && MI2.mayLoad())) { in apply() 276 if (!L0.mayLoad() || L0.mayStore() || in apply() 289 if (!L1.mayLoad() || L1.mayStore() || in apply()
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| /freebsd-12.1/contrib/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfoC.td | 211 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in 217 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in 223 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in 229 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in 235 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 249 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 260 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 350 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 364 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, 373 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in [all …]
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| H A D | RISCVInstrInfoA.td | 19 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in 34 let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in 151 let mayStore = 1; 174 let mayStore = 1; 185 let mayStore = 1; 195 let mayStore = 1; 241 let mayStore = 1; 269 let mayStore = 1;
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| H A D | RISCVInstrInfoF.td | 37 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 47 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 52 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 62 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 68 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 80 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 90 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in 98 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
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| H A D | RISCVInstrInfo.td | 240 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 249 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in 257 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in 263 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 268 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 274 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 279 let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in 284 let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in 290 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 325 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0 [all …]
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| H A D | RISCVInstrInfoD.td | 33 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 43 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 48 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 58 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 69 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in 77 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/ |
| H A D | ImplicitNullChecks.cpp | 325 if (!(PrevMI->mayStore() || PrevMI->mayLoad())) in areMemoryOpsAliased() 328 if (!(MI.mayStore() || PrevMI->mayStore())) in areMemoryOpsAliased() 333 return MI.mayStore() ? AR_WillAliasEverything : AR_MayAlias; in areMemoryOpsAliased() 335 return PrevMI->mayStore() ? AR_WillAliasEverything : AR_MayAlias; in areMemoryOpsAliased() 371 if (!((MI.mayLoad() || MI.mayStore()) && !MI.isPredicable() && in isSuitableMemoryOp() 630 MI->mayStore() ? FaultMaps::FaultingLoadStore : FaultMaps::FaultingLoad; in insertFaultingInstr()
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | SIMemoryLegalizer.cpp | 535 if (!(MI->mayLoad() && !MI->mayStore())) in getLoadInfo() 549 if (!(!MI->mayLoad() && MI->mayStore())) in getStoreInfo() 596 if (!(MI->mayLoad() && MI->mayStore())) in getAtomicCmpxchgOrRmwInfo() 623 assert(MI->mayLoad() && !MI->mayStore()); in enableLoadCacheBypass() 657 assert(MI->mayLoad() ^ MI->mayStore()); in enableNonTemporal() 867 assert(MI->mayLoad() && !MI->mayStore()); in expandLoad() 912 assert(!MI->mayLoad() && MI->mayStore()); in expandStore() 977 assert(MI->mayLoad() && MI->mayStore()); in expandAtomicCmpxchgOrRmw()
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| H A D | SMInstructions.td | 32 let mayStore = 0; 69 let mayStore = 0; 82 let mayStore = 0; 91 let mayStore = 1; 99 let mayStore = 0; 161 let mayStore = 0; 170 let mayStore = 1; 192 let mayStore = 1; 640 let mayStore = ps.mayStore;
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| H A D | SIInsertWaitcnts.cpp | 528 if (TII->isDS(Inst) && (Inst.mayStore() || Inst.mayLoad())) { in updateByEvent() 538 if (Inst.mayStore()) { in updateByEvent() 570 if (Inst.mayStore()) { in updateByEvent() 582 if (Inst.mayStore()) { in updateByEvent() 591 if (Inst.mayStore()) { in updateByEvent() 595 if (Inst.mayStore()) { in updateByEvent() 647 if (TII->isDS(Inst) && Inst.mayStore()) { in updateByEvent() 965 if (MI.mayStore()) { in generateWaitcntInstBefore() 1107 assert(Inst.mayLoad() || Inst.mayStore()); in updateEventWaitcntAfter() 1128 (Inst.mayStore() || AMDGPU::getAtomicNoRetOp(Inst.getOpcode()) != -1)) { in updateEventWaitcntAfter()
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| H A D | SIInstrFormats.td | 79 // on wave termination. It is necessary to distinguish from mayStore 224 let mayStore = 0; 326 let mayStore = 0; 336 let mayStore = 1;
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| /freebsd-12.1/contrib/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrSystem.td | 140 let hasSideEffects = 1, mayStore = 1, Uses = [R0D], Defs = [R0D, CC] in 144 let mayLoad = 1, mayStore = 1, Defs = [CC] in { 195 let mayStore = 1 in { 209 let mayLoad = 1, mayStore = 1, Defs = [CC] in 213 let mayLoad = 1, mayStore = 1, Defs = [CC] in { 219 let mayLoad = 1, mayStore = 1, Uses = [R0L, R1L] in { 225 let mayLoad = 1, mayStore = 1, Uses = [R0L] in 229 let mayLoad = 1, mayStore = 1, Uses = [R0L], Defs = [CC] in
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| H A D | SystemZInstrBuilder.h | 35 if (MCID.mayStore()) in addFrameReference()
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| /freebsd-12.1/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsEVAInstrInfo.td | 82 bit mayStore = 1; 103 bit mayStore = 0; 119 bit mayStore = 1; 147 bit mayStore = 1;
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| H A D | MipsDelaySlotFiller.cpp | 453 if (!MI.mayStore() && !MI.mayLoad()) in hasHazard() 462 SeenStore |= MI.mayStore(); in hasHazard() 475 if (MI.mayStore()) in hasHazard_() 502 HasHazard |= updateDefsUses(*I, MI.mayStore()); in hasHazard_() 508 HasHazard = MI.mayStore() && (OrigSeenLoad || OrigSeenStore); in hasHazard_() 512 SeenNoObjStore |= MI.mayStore(); in hasHazard_()
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| /freebsd-12.1/contrib/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyInstrInfo.td | 231 // by the ExplicitLocals pass. It has mayStore because it writes to a wasm 233 let mayStore = 1, isAsCheapAsAMove = 1 in 239 // LOCAL_TEEs by the ExplicitLocals pass. It has mayStore for the same reason 241 let mayStore = 1, isAsCheapAsAMove = 1 in 257 let mayStore = 1 in
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrFormats.td | 3622 let mayStore = 0, mayLoad = 1 in 3631 let mayStore = 1, mayLoad = 0 in 3668 let mayStore = 0, mayLoad = 1 in 3677 let mayStore = 1, mayLoad = 0 in 3766 let mayStore = 0, mayLoad = 1 in 3774 let mayStore = 1, mayLoad = 0 in 3807 let mayStore = 0, mayLoad = 1 in 3815 let mayStore = 1, mayLoad = 0 in 3925 let mayLoad = 1, mayStore = 0 in 3956 let mayLoad = 0, mayStore = 1 in [all …]
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| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonShuffler.cpp | 157 setStore(HexagonMCInstrInfo::getDesc(MCII, *id).mayStore()); in HexagonCVIResource() 271 if (HexagonMCInstrInfo::getDesc(MCII, Inst).mayStore()) { in restrictNoSlot1Store() 388 assert(HexagonMCInstrInfo::getDesc(MCII, ID).mayStore()); in check() 472 if (HexagonMCInstrInfo::getDesc(MCII, ID).mayStore()) { in check()
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| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86InstrVMX.td | 59 let mayStore = 1 in { 66 } // mayStore
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMOptimizeBarriersPass.cpp | 45 MI->mayStore() || in CanMovePastDMB()
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