Home
last modified time | relevance | path

Searched refs:link_width_cntl (Results 1 – 4 of 4) sorted by relevance

/freebsd-12.1/sys/dev/drm2/radeon/
H A Drv770.c1224 u32 link_width_cntl, lanes, speed_cntl, tmp; in rv770_pcie_gen2_enable() local
1252 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); in rv770_pcie_gen2_enable()
1253 link_width_cntl &= ~LC_UPCONFIGURE_DIS; in rv770_pcie_gen2_enable()
1254 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in rv770_pcie_gen2_enable()
1255 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); in rv770_pcie_gen2_enable()
1256 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { in rv770_pcie_gen2_enable()
1258 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | in rv770_pcie_gen2_enable()
1260 link_width_cntl |= lanes | LC_RECONFIG_NOW | in rv770_pcie_gen2_enable()
1264 link_width_cntl |= LC_UPCONFIGURE_DIS; in rv770_pcie_gen2_enable()
1301 link_width_cntl |= LC_UPCONFIGURE_DIS; in rv770_pcie_gen2_enable()
[all …]
H A Dr300.c471 uint32_t link_width_cntl, mask; in rv370_set_pcie_lanes() local
506 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()
508 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == in rv370_set_pcie_lanes()
512 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | in rv370_set_pcie_lanes()
516 link_width_cntl |= mask; in rv370_set_pcie_lanes()
517 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in rv370_set_pcie_lanes()
518 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | in rv370_set_pcie_lanes()
522 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()
523 while (link_width_cntl == 0xffffffff) in rv370_set_pcie_lanes()
530 u32 link_width_cntl; in rv370_get_pcie_lanes() local
[all …]
H A Dr600.c4144 u32 link_width_cntl, mask, target_reg; in r600_set_pcie_lanes() local
4196 link_width_cntl |= mask; in r600_set_pcie_lanes()
4218 link_width_cntl = RREG32(target_reg); in r600_set_pcie_lanes()
4219 while (link_width_cntl == 0xffffffff) in r600_set_pcie_lanes()
4220 link_width_cntl = RREG32(target_reg); in r600_set_pcie_lanes()
4226 u32 link_width_cntl; in r600_get_pcie_lanes() local
4304 link_width_cntl &= ~LC_UPCONFIGURE_DIS; in r600_pcie_gen2_enable()
4309 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | in r600_pcie_gen2_enable()
4314 link_width_cntl |= LC_UPCONFIGURE_DIS; in r600_pcie_gen2_enable()
4371 link_width_cntl |= LC_UPCONFIGURE_DIS; in r600_pcie_gen2_enable()
[all …]
H A Devergreen.c3805 u32 link_width_cntl, speed_cntl, mask; in evergreen_pcie_gen2_enable() local
3839 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); in evergreen_pcie_gen2_enable()
3840 link_width_cntl &= ~LC_UPCONFIGURE_DIS; in evergreen_pcie_gen2_enable()
3841 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in evergreen_pcie_gen2_enable()
3860 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); in evergreen_pcie_gen2_enable()
3863 link_width_cntl |= LC_UPCONFIGURE_DIS; in evergreen_pcie_gen2_enable()
3865 link_width_cntl &= ~LC_UPCONFIGURE_DIS; in evergreen_pcie_gen2_enable()
3866 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in evergreen_pcie_gen2_enable()