| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | Thumb2InstrInfo.cpp | 246 bool isSub = NumBytes < 0; in emitT2RegPlusImmediate() local
247 if (isSub) NumBytes = -NumBytes; in emitT2RegPlusImmediate()
271 if (isSub) { in emitT2RegPlusImmediate()
478 bool isSub = false; in rewriteT2FrameIndex() local
505 isSub = true; in rewriteT2FrameIndex()
580 isSub = true; in rewriteT2FrameIndex()
598 isSub = true; in rewriteT2FrameIndex()
612 isSub = true; in rewriteT2FrameIndex()
641 if (isSub) { in rewriteT2FrameIndex()
655 if (isSub) { in rewriteT2FrameIndex()
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| H A D | ThumbRegisterInfo.cpp | 133 bool isSub = false; in emitThumbRegPlusImmInReg() local
139 isSub = true; in emitThumbRegPlusImmInReg()
170 int Opc = (isSub) ? ARM::tSUBrr in emitThumbRegPlusImmInReg()
175 if (DestReg == ARM::SP || isSub) in emitThumbRegPlusImmInReg()
193 bool isSub = NumBytes < 0; in emitThumbRegPlusImmediate() local
195 if (isSub) Bytes = -NumBytes; in emitThumbRegPlusImmediate()
228 ExtraOpc = isSub ? ARM::tSUBspi : ARM::tADDspi; in emitThumbRegPlusImmediate()
234 assert(!isSub && "Thumb1 does not have tSUBrSPi"); in emitThumbRegPlusImmediate()
243 CopyOpc = isSub ? ARM::tSUBi3 : ARM::tADDi3; in emitThumbRegPlusImmediate()
251 ExtraOpc = isSub ? ARM::tSUBi8 : ARM::tADDi8; in emitThumbRegPlusImmediate()
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| H A D | ARMBaseInstrInfo.cpp | 2389 bool isSub = false; in rewriteARMFrameIndex() local
2406 isSub = true; in rewriteARMFrameIndex()
2484 isSub = true; in rewriteARMFrameIndex()
2499 if (isSub) { in rewriteARMFrameIndex()
2512 if (isSub) { in rewriteARMFrameIndex()
3145 if (!isSub && in getNumMicroOpsSwiftLdSt()
3161 if (!isSub && in getNumMicroOpsSwiftLdSt()
3189 if (!isSub && in getNumMicroOpsSwiftLdSt()
3202 if (!isSub && in getNumMicroOpsSwiftLdSt()
3253 if (!isSub && in getNumMicroOpsSwiftLdSt()
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| H A D | ARMISelLowering.cpp | 9267 bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub; in EmitInstrWithCustomInserter() local
9269 if (isSub) in EmitInstrWithCustomInserter()
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMAddressingModes.h | 401 bool isSub = Opc == sub; variable
402 return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ;
432 bool isSub = Opc == sub; variable
433 return ((int)isSub << 8) | Offset | (IdxMode << 9);
475 bool isSub = Opc == sub; in getAM5Opc() local
476 return ((int)isSub << 8) | Offset; in getAM5Opc()
496 bool isSub = Opc == sub; in getAM5FP16Opc() local
497 return ((int)isSub << 8) | Offset; in getAM5FP16Opc()
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| /freebsd-12.1/contrib/llvm/lib/Target/RISCV/ |
| H A D | RISCVFrameLowering.cpp | 71 bool isSub = Val < 0; in adjustReg() local
72 if (isSub) { in adjustReg()
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/InstPrinter/ |
| H A D | ARMInstPrinter.cpp | 351 bool isSub = OffImm < 0; in printThumbLdrLabelOperand() local
356 if (isSub) { in printThumbLdrLabelOperand()
1129 bool isSub = OffImm < 0; in printAddrModeImm12Operand() local
1133 if (isSub) { in printAddrModeImm12Operand()
1153 bool isSub = OffImm < 0; in printT2AddrModeImm8Operand() local
1157 if (isSub) { in printT2AddrModeImm8Operand()
1182 bool isSub = OffImm < 0; in printT2AddrModeImm8s4Operand() local
1189 if (isSub) { in printT2AddrModeImm8s4Operand()
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| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86FrameLowering.cpp | 254 bool isSub = NumBytes < 0; in emitSPUpdate() local
255 uint64_t Offset = isSub ? -NumBytes : NumBytes; in emitSPUpdate()
257 isSub ? MachineInstr::FrameSetup : MachineInstr::FrameDestroy; in emitSPUpdate()
267 if (isSub && !isEAXLiveIn(MBB)) in emitSPUpdate()
274 isSub ? getSUBrrOpcode(Is64Bit) : getADDrrOpcode(Is64Bit); in emitSPUpdate()
298 if (isSub) in emitSPUpdate()
325 unsigned Reg = isSub in emitSPUpdate()
329 unsigned Opc = isSub in emitSPUpdate()
333 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub)) in emitSPUpdate()
340 BuildStackAdjustment(MBB, MBBI, DL, isSub ? -ThisVal : ThisVal, InEpilogue) in emitSPUpdate()
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrFormats.td | 1713 let Inst{30} = isSub;
1723 : BaseBaseAddSubCarry<isSub, regtype, asm,
1728 : BaseBaseAddSubCarry<isSub, regtype, asm,
1839 let Inst{15} = isSub;
1862 : BaseMulAccum<isSub, opc, GPR32, GPR64, asm,
2025 let Inst{30} = isSub;
2065 let Inst{30} = isSub;
2090 let Inst{30} = isSub;
2115 let Inst{30} = isSub;
2246 def Wrx : BaseAddSubEReg<isSub, 1, GPR32, GPR32sp,
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| H A D | AArch64InstrInfo.cpp | 2890 bool isSub = Offset < 0; in emitFrameOffset() local
2891 if (isSub) in emitFrameOffset()
2907 Opc = isSub ? AArch64::SUBSXri : AArch64::ADDSXri; in emitFrameOffset()
2909 Opc = isSub ? AArch64::SUBXri : AArch64::ADDXri; in emitFrameOffset()
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| /freebsd-12.1/contrib/llvm/tools/clang/lib/CodeGen/ |
| H A D | CGExprScalar.cpp | 3280 bool isSub=false) { in tryEmitFMulAdd() argument
3296 return buildFMulAdd(LHSBinOp, op.RHS, CGF, Builder, false, isSub); in tryEmitFMulAdd()
3301 return buildFMulAdd(RHSBinOp, op.LHS, CGF, Builder, isSub, false); in tryEmitFMulAdd()
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