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Searched refs:isPredicated (Results 1 – 25 of 44) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonDepInstrInfo.td629 let isPredicated = 1;
645 let isPredicated = 1;
661 let isPredicated = 1;
681 let isPredicated = 1;
702 let isPredicated = 1;
721 let isPredicated = 1;
742 let isPredicated = 1;
757 let isPredicated = 1;
773 let isPredicated = 1;
787 let isPredicated = 1;
[all …]
H A DHexagonVLIWPacketizer.cpp359 return HII->isPredicated(MI) && HII->getDotNewPredOp(MI, nullptr) > 0; in isNewifiable()
561 if (!HII->isPredicated(MI)) in getPredicateSense()
692 if (HII->isPredicated(PacketMI)) { in canPromoteToNewValueStore()
693 if (!HII->isPredicated(MI)) in canPromoteToNewValueStore()
917 if (!HII->isPredicated(*I)) in restrictingDepExistInPacket()
944 assert(QII->isPredicated(MI) && "Must be predicated instruction"); in getPredicatedRegister()
1199 if (HII->isPredicated(I) || HII->isPredicated(J)) in hasDeadDependence()
1239 if (HII->isPredicated(MI) && HII->isPredicatedNew(MI) && HII->isJumpR(MI)) in hasControlDependence()
1460 if (HII->isPredicated(I) && HII->isPredicated(J) && in isLegalToPacketizeTogether()
H A DHexagonInstrFormatsV5.td55 bits<1> isPredicated = 0;
56 let TSFlags{7} = isPredicated;
H A DHexagonExpandCondsets.cpp343 if (HII->isPredicated(*DefI)) in updateKillFlags()
421 if (HII->isPredicated(*DefI)) in updateDeadsInRange()
491 if (!HII->isPredicated(*DefI)) in updateDeadsInRange()
723 if (HII->isPredicated(*MI) || !HII->isPredicable(*MI)) in isPredicable()
758 if (PredValid && HII->isPredicated(*MI)) { in getReachingDefForPred()
916 if (!HII->isPredicated(*MI)) in renameInRange()
989 if (PredValid && HII->isPredicated(*MI) && MI->readsRegister(PredR)) in predicate()
H A DHexagonInstrFormats.td85 bits<1> isPredicated = 0;
86 let TSFlags{10} = isPredicated;
180 let PredSense = !if(isPredicated, !if(isPredicatedFalse, "false", "true"),
H A DHexagonInstrInfo.h233 bool isPredicated(const MachineInstr &MI) const override;
396 bool isPredicated(unsigned Opcode) const;
H A DHexagonPeephole.cpp239 if (QII->isPredicated(MI)) { in runOnMachineFunction()
H A DHexagon.td287 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
295 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
H A DHexagonInstrInfo.cpp606 if (Term != MBB.end() && isPredicated(*Term) && in insertBranch()
1514 bool HexagonInstrInfo::isPredicated(const MachineInstr &MI) const { in isPredicated() function in HexagonInstrInfo
2090 if (isNewValueInst(MI) || (isPredicated(MI) && isPredicatedNew(MI))) in isDotNewInst()
2374 return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode); in isNewValueJump()
2397 assert(isPredicated(MI)); in isPredicatedNew()
2403 assert(isPredicated(Opcode)); in isPredicatedNew()
2421 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const { in isPredicated() function in HexagonInstrInfo
3099 if (Cond.empty() || !isPredicated(Cond[0].getImm())) in predOpcodeHasNot()
3164 if (isPredicated(MI)) { in getBaseAndOffsetPosition()
3631 if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form in getDotOldOp()
/freebsd-12.1/contrib/llvm/lib/Target/ARC/
H A DARCInstrInfo.cpp169 while (isPredicated(*I) || I->isTerminator() || I->isDebugValue()) { in analyzeBranch()
201 CantAnalyze = !isPredicated(*I); in analyzeBranch()
209 if (!isPredicated(*I) && (isUncondBranchOpcode(I->getOpcode()) || in analyzeBranch()
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DIfConversion.cpp988 bool isPredicated = TII->isPredicated(MI); in ScanInstructions() local
1000 if (!isPredicated) { in ScanInstructions()
1015 if (BBI.ClobbersPred && !isPredicated) { in ScanInstructions()
1862 bool BB1Predicated = BBI1T != MBB1.end() && TII->isPredicated(*BBI1T); in IfConvertDiamondCommon()
1863 bool BB2NonPredicated = BBI2T != MBB2.end() && !TII->isPredicated(*BBI2T); in IfConvertDiamondCommon()
1954 if (TI != BBI.BB->end() && TII->isPredicated(*TI)) in IfConvertDiamond()
2012 if (I.isDebugInstr() || TII->isPredicated(I)) in PredicateBlock()
2068 if (!TII->isPredicated(I) && !MI->isDebugInstr()) { in CopyAndPredicateBlock()
2122 if (FromTI != FromMBB.end() && !TII->isPredicated(*FromTI)) in MergeBlocks()
H A DCriticalAntiDepBreaker.cpp184 MI.isCall() || MI.hasExtraSrcRegAllocReq() || TII->isPredicated(MI); in PrescanInstruction()
259 if (!TII->isPredicated(MI)) { in ScanInstruction()
604 if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI)) in BreakAntiDependencies()
H A DTargetSchedule.cpp307 if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(*DepMI)) in computeOutputLatency()
H A DAggressiveAntiDepBreaker.cpp390 if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI) || in PrescanInstruction()
468 TII->isPredicated(MI) || MI.isInlineAsm(); in ScanInstruction()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.h267 bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI);
301 bool isPredicated() const;
H A DHexagonMCChecker.cpp70 if (HexagonMCInstrInfo::isPredicated(MCII, MCI) && isPredicateRegister(R)) { in initReg()
427 if (std::get<2>(Producer).isPredicated() && in checkNewValues()
428 (!Consumer.isPredicated() || in checkNewValues()
H A DHexagonMCInstrInfo.cpp36 bool HexagonMCInstrInfo::PredicateInfo::isPredicated() const { in isPredicated() function in HexagonMCInstrInfo::PredicateInfo
630 bool HexagonMCInstrInfo::isPredicated(MCInstrInfo const &MCII, in isPredicated() function in HexagonMCInstrInfo
820 if (!isPredicated(MCII, MCI)) in predicateInfo()
/freebsd-12.1/contrib/llvm/lib/Analysis/
H A DVectorUtils.cpp841 (!isPredicated(B->getParent()) || EnablePredicatedInterleavedMemAccesses)) { in analyzeInterleaving()
939 if ((isPredicated(BlockA) || isPredicated(BlockB)) && in analyzeInterleaving()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp359 CantAnalyze = !isPredicated(*I); in analyzeBranch()
367 if (!isPredicated(*I) && in analyzeBranch()
483 bool ARMBaseInstrInfo::isPredicated(const MachineInstr &MI) const { in isPredicated() function in ARMBaseInstrInfo
2733 isPredicated(*PotentialAND)) in optimizeCompareInstr()
2845 if (isPredicated(*MI)) in optimizeCompareInstr()
2984 if (isPredicated(MI)) in shouldSink()
4610 if (MI.getOpcode() == ARM::VMOVD && !isPredicated(MI)) in getExecutionDomain()
4615 if (Subtarget.useNEONForFPMovs() && !isPredicated(MI) && in getExecutionDomain()
4709 assert(!isPredicated(MI) && "Cannot predicate a VORRd"); in setExecutionDomain()
4731 assert(!isPredicated(MI) && "Cannot predicate a VGETLN"); in setExecutionDomain()
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H A DARMBaseInstrInfo.h149 bool isPredicated(const MachineInstr &MI) const override;
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.h181 bool isPredicated(const MachineInstr &MI) const override;
H A DR600Packetizer.cpp85 if (TII->isPredicated(*BI)) in getPreviousVector()
/freebsd-12.1/contrib/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp173 return !isPredicated(MI); in isUnpredicatedTerminator()
/freebsd-12.1/contrib/llvm/include/llvm/Analysis/
H A DVectorUtils.h530 bool isPredicated(BasicBlock *BB) const { in isPredicated() function
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h341 bool isPredicated(const MachineInstr &MI) const override;

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