Searched refs:isInsertSubreg (Results 1 – 14 of 14) sorted by relevance
105 } else if (DefMI->isInsertSubreg()) { in getAccDefMI()128 while (UseMI->isCopy() || UseMI->isInsertSubreg()) { in getDefReg()171 } else if (DefMI->isInsertSubreg()) { in hasLoopHazard()
248 if (MI->isInsertSubreg()) { in optimizeSDPattern()331 if (MI->isInsertSubreg() && usesRegClass(MI->getOperand(2), in hasPartialWrite()399 if (MI->isCopyLike() || MI->isInsertSubreg() || MI->isRegSequence() || in getReadDPRs()
4061 if (ResolvedDefMI->isCopyLike() || ResolvedDefMI->isInsertSubreg() || in getOperandLatency()4398 if (MI.isCopyLike() || MI.isInsertSubreg() || MI.isRegSequence() || in getPredicationCost()4419 if (MI.isCopyLike() || MI.isInsertSubreg() || MI.isRegSequence() || in getInstrLatency()
6254 let isInsertSubreg = 1;
65 !MI->isInsertSubreg() && in canTurnIntoImplicitDef()
241 (MI.isRegSequence() || MI.isInsertSubreg() || in isCoalescableCopy()907 assert(MI.isInsertSubreg() && "Invalid instruction"); in InsertSubregRewriter()1920 assert((Def->isInsertSubreg() || Def->isInsertSubregLike()) && in getNextSourceFromInsertSubreg()2063 if (Def->isInsertSubreg() || Def->isInsertSubregLike()) in getNextSourceImpl()
1197 assert((MI.isInsertSubreg() || in getInsertSubregInputs()1200 if (!MI.isInsertSubreg()) in getInsertSubregInputs()
416 } else if (MI.isInsertSubreg() || MI.isSubregToReg()) { in isCopyToReg()1763 if (mi->isInsertSubreg()) { in runOnMachineFunction()
138 FLAG(isInsertSubreg) in EmitInstrDocs()
272 bool isInsertSubreg : 1; variable
625 if (Inst.isInsertSubreg) OS << "|(1ULL<<MCID::InsertSubreg)"; in emitRecord()
369 isInsertSubreg = R->getValueAsBit("isInsertSubreg"); in CodeGenInstruction()
434 if (isInsertSubreg() && OpIdx == 3)1024 bool isInsertSubreg() const {
479 bit isInsertSubreg = 0; // Is this instruction a kind of insert subreg?