| /freebsd-12.1/contrib/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCCodeEmitter.cpp | 576 isAdd = false; in EncodeAddrModeOpValues()
582 isAdd = false; in EncodeAddrModeOpValues()
586 return isAdd; in EncodeAddrModeOpValues()
926 if (isAdd) in getAddrModeImm12OpValue()
959 if (isAdd) in getT2Imm8s4OpValue()
999 if (isAdd) in getT2AddrModeImm8s4OpValue()
1105 if (isAdd) in getLdStSORegOpValue()
1252 bool isAdd; in getAddrMode5OpValue() local
1277 if (isAdd) in getAddrMode5OpValue()
1292 bool isAdd; in getAddrMode5FP16OpValue() local
[all …]
|
| H A D | ARMAsmBackend.cpp | 432 bool isAdd = true; in adjustFixupValue() local
435 isAdd = false; in adjustFixupValue()
441 Value |= isAdd << 23; in adjustFixupValue()
661 bool isAdd = true; in adjustFixupValue() local
664 isAdd = false; in adjustFixupValue()
681 bool isAdd = true; in adjustFixupValue() local
684 isAdd = false; in adjustFixupValue()
692 Value |= isAdd << 23; in adjustFixupValue()
708 bool isAdd = true; in adjustFixupValue() local
711 isAdd = false; in adjustFixupValue()
[all …]
|
| /freebsd-12.1/contrib/llvm/utils/TableGen/ |
| H A D | InstrDocsEmitter.cpp | 112 FLAG(isAdd) in EmitInstrDocs()
|
| H A D | CodeGenInstruction.h | 246 bool isAdd : 1; variable
|
| H A D | InstrInfoEmitter.cpp | 598 if (Inst.isAdd) OS << "|(1ULL<<MCID::Add)"; in emitRecord()
|
| H A D | CodeGenInstruction.cpp | 354 isAdd = R->getValueAsBit("isAdd"); in CodeGenInstruction()
|
| /freebsd-12.1/contrib/llvm/include/llvm/MC/ |
| H A D | MCInstrDesc.h | 249 bool isAdd() const { return Flags & (1ULL << MCID::Add); } in isAdd() function
|
| /freebsd-12.1/contrib/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 761 bool isAdd; member
2667 bool isAdd = Imm >= 0; in addPostIdxImm8Operands() local
2669 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; in addPostIdxImm8Operands()
2678 bool isAdd = Imm >= 0; in addPostIdxImm8s4Operands() local
2681 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; in addPostIdxImm8s4Operands()
2688 Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd)); in addPostIdxRegOperands()
3145 Op->PostIdxReg.isAdd = isAdd; in CreatePostIdxReg()
4880 bool isAdd = true; in parsePostIdxReg() local
4886 isAdd = false; in parsePostIdxReg()
4962 bool isAdd = true; in parseAM3Offset() local
[all …]
|
| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMInstrInfo.td | 2824 // {12} isAdd
2843 // {12} isAdd
2860 // {12} isAdd
2879 // {12} isAdd
3147 // {12} isAdd
3166 // {12} isAdd
3188 // {12} isAdd
3207 // {12} isAdd
3636 let isAdd = 1 in
3652 let isAdd = 1 in
[all …]
|
| H A D | ARMInstrFormats.td | 693 // {12} isAdd
711 // {12} isAdd
732 // {12} isAdd
785 // {8} isAdd
|
| H A D | ARMBaseInstrInfo.cpp | 601 bool isAdd = ARM_AM::getAM2Op(OffImm) == ARM_AM::add; in isLdstScaledRegNotPlusLsl2() local
605 bool SimpleScaled = (isAdd && ShiftOpc == ARM_AM::lsl && Amt == 2); in isLdstScaledRegNotPlusLsl2()
|
| H A D | ARMInstrThumb.td | 925 let isAdd = 1 in {
|
| H A D | ARMInstrThumb2.td | 2080 let isAdd = 1 in
|
| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonHardwareLoops.cpp | 442 if (DI->getDesc().isAdd()) { in findInductionRegister()
1641 if (DI->getDesc().isAdd()) { in fixupInductionVariable()
|
| H A D | HexagonDepInstrInfo.td | 222 let isAdd = 1;
238 let isAdd = 1;
|
| /freebsd-12.1/contrib/llvm/include/llvm/Target/ |
| H A D | Target.td | 451 bit isAdd = 0; // Is this instruction an add instruction?
|
| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 35171 auto combineMulShlAddOrSub = [&](int Mult, int Shift, bool isAdd) { in combineMulSpecial() argument
35176 Result = DAG.getNode(isAdd ? ISD::ADD : ISD::SUB, DL, VT, Result, in combineMulSpecial()
35181 auto combineMulMulAddOrSub = [&](int Mul1, int Mul2, bool isAdd) { in combineMulSpecial() argument
35186 Result = DAG.getNode(isAdd ? ISD::ADD : ISD::SUB, DL, VT, Result, in combineMulSpecial()
|