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Searched refs:is128BitVector (Results 1 – 14 of 14) sorted by relevance

/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DValueTypes.h182 bool is128BitVector() const { in is128BitVector() function
183 return isSimple() ? V.is128BitVector() : isExtended128BitVector(); in is128BitVector()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.h98 else if (LocVT.SimpleTy == MVT::f128 || LocVT.is128BitVector()) in CC_AArch64_Custom_Block()
H A DAArch64TargetTransformInfo.cpp626 LT.second.is128BitVector() && Alignment < 16) { in getMemoryOpCost()
H A DAArch64FastISel.cpp2964 VT.is128BitVector()) in fastLowerArguments()
3010 } else if (VT.is128BitVector()) { in fastLowerArguments()
H A DAArch64ISelLowering.cpp2530 assert(ExtTy.is128BitVector() && "Unexpected extension size"); in addRequiredExtensionForVectorMULL()
2646 assert(VT.is128BitVector() && VT.isInteger() && in LowerMUL()
3094 else if (RegVT == MVT::f128 || RegVT.is128BitVector()) in LowerFormalArguments()
7587 (VT.is128BitVector() || VT.is64BitVector())) { in isShuffleMaskLegal()
9783 if (!VT.is128BitVector()) { in performAddSubLongCombine()
H A DAArch64ISelDAGToDAG.cpp1159 } else if (VT.is128BitVector()) { in tryIndexedLoad()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp7026 if (!VT.is128BitVector()) in LowerBuildVectorv4x32()
10848 assert(VT.is128BitVector() && in lowerVectorShuffleAsByteRotate()
11541 if (!VT.is128BitVector()) in lowerVectorShuffleAsElementInsertion()
11972 assert(VT.is128BitVector() && in lowerVectorShuffleAsPermuteAndUnpack()
16139 if (VT.is128BitVector()) in lowerVectorShuffle()
16664 if (!OpVT.is128BitVector()) { in LowerSCALAR_TO_VECTOR()
18156 if (SrcVT.is128BitVector()) { in truncateVectorWithPACK()
20363 assert(VT.is128BitVector() && InVT.is128BitVector() && "Unexpected VTs"); in LowerEXTEND_VECTOR_INREG()
25607 assert(VT.is128BitVector() && in LowerBITREVERSE_XOP()
30587 if (MaskVT.is128BitVector()) { in matchBinaryVectorShuffle()
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H A DX86ISelDAGToDAG.cpp493 if (OpVT.is256BitVector() || OpVT.is128BitVector()) in isLegalMaskCompare()
3384 if (NVT.is512BitVector() || NVT.is256BitVector() || NVT.is128BitVector() || in Select()
H A DX86FastISel.cpp3678 if (!SVT.is128BitVector() && in fastSelectInstruction()
/freebsd-12.1/contrib/llvm/include/llvm/Support/
H A DMachineValueType.h351 bool is128BitVector() const { in is128BitVector() function
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp601 if (!Ty.is128BitVector()) in performORCombine()
993 if (Subtarget.hasMSA() && Ty.is128BitVector() && Ty.isInteger()) { in performXORCombine()
2377 if (!VecTy.is128BitVector()) in lowerEXTRACT_VECTOR_ELT()
2429 if (!Subtarget.hasMSA() || !ResTy.is128BitVector()) in lowerBUILD_VECTOR()
2949 if (!ResTy.is128BitVector()) in lowerVECTOR_SHUFFLE()
H A DMipsSEISelDAGToDAG.cpp1043 if (!Subtarget->hasMSA() || !BVN->getValueType(0).is128BitVector()) in trySelect()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp5253 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32; in getZeroVector()
6369 DAG, dl, VmovVT, VT.is128BitVector(), in LowerBUILD_VECTOR()
6380 DAG, dl, VmovVT, VT.is128BitVector(), in LowerBUILD_VECTOR()
6525 if (VT.is128BitVector() && VT != MVT::v2f64 && VT != MVT::v4f32) { in LowerBUILD_VECTOR()
6786 (VT.is128BitVector() || VT.is64BitVector())) { in isShuffleMaskLegal()
7136 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 && in LowerCONCAT_VECTORS()
7254 assert(ExtTy.is128BitVector() && "Unexpected extension size"); in AddRequiredExtensionForVMULL()
7369 assert(VT.is128BitVector() && VT.isInteger() && in LowerMUL()
9833 !N0.getValueType().is128BitVector()) in AddCombineVUZPToVPADDL()
10621 if (VT.is64BitVector() || VT.is128BitVector()) in PerformMULCombine()
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/freebsd-12.1/contrib/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp1127 assert(VecType.is128BitVector() && "Unexpected shuffle vector type"); in LowerVECTOR_SHUFFLE()