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Searched refs:hasVGPRs (Results 1 – 8 of 8) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp154 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg()))) in hasVGPROperands()
187 TRI.hasVGPRs(SrcRC); in isVGPRToSGPRCopy()
194 TRI.hasVGPRs(DstRC); in isSGPRToVGPRCopy()
312 if (TRI->hasVGPRs(MRI.getRegClass(Reg))) in phiHasVGPROperands()
685 if (TRI->hasVGPRs(TII->getOpRegClass(MI, 0)) || in runOnMachineFunction()
701 (TRI->hasVGPRs(Src0RC) || TRI->hasVGPRs(Src1RC))) { in runOnMachineFunction()
H A DSIRegisterInfo.h133 return !hasVGPRs(RC); in isSGPRClass()
151 bool hasVGPRs(const TargetRegisterClass *RC) const;
H A DSIFixupVectorISel.cpp145 if (!TRI->hasVGPRs(MRI.getRegClass(IndexReg))) in findSRegBaseAndIndex()
H A DSIInstrInfo.cpp923 assert(RI.hasVGPRs(RC) && "Only VGPR spilling expected"); in storeRegToStackSlot()
1017 assert(RI.hasVGPRs(RC) && "Only VGPR spilling expected"); in loadRegFromStackSlot()
2914 if (!MO.isReg() || !RI.hasVGPRs(RI.getRegClassForReg(MRI, MO.getReg()))) { in verifyInstruction()
3283 return RI.hasVGPRs(getOpRegClass(MI, 0)); in canReadVGPR()
3285 return RI.hasVGPRs(getOpRegClass(MI, OpNo)); in canReadVGPR()
3915 if (RI.hasVGPRs(OpRC)) { in legalizeOperands()
3957 if (RI.hasVGPRs(DstRC)) { in legalizeOperands()
3997 if (Src.isReg() && RI.hasVGPRs(MRI.getRegClass(Src.getReg()))) in legalizeOperands()
5061 if (RI.hasVGPRs(NewDstRC)) in getDestEquivalentVGPRClass()
H A DSIRegisterInfo.cpp1258 bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const { in hasVGPRs() function in SIRegisterInfo
1512 return hasVGPRs(RC); in isVGPR()
H A DSIWholeQuadMode.cpp389 TRI->hasVGPRs(TRI->getPhysRegClass(Reg))) { in scanInstructions()
H A DSIFoldOperands.cpp461 if (TRI->isSGPRClass(SrcRC) && TRI->hasVGPRs(DestRC)) { in foldOperand()
H A DSIPeepholeSDWA.cpp1171 !TRI->hasVGPRs(TRI->getRegClass(Desc.OpInfo[I].RegClass))) in legalizeScalarOperands()