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Searched refs:gtt_offset (Results 1 – 16 of 16) sorted by relevance

/freebsd-12.1/sys/dev/drm2/i915/
H A Di915_gem_tiling.c271 if (obj->gtt_offset & ~I915_FENCE_START_MASK) in i915_gem_object_fence_ok()
274 if (obj->gtt_offset & ~I830_FENCE_START_MASK) in i915_gem_object_fence_ok()
293 if (obj->gtt_offset & (size - 1)) in i915_gem_object_fence_ok()
374 (obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end && in i915_gem_set_tiling()
383 if (obj->gtt_offset & (unfenced_alignment - 1)) in i915_gem_set_tiling()
H A Dintel_ringbuffer.c47 u32 gtt_offset; member
183 u32 scratch_addr = pc->gtt_offset + 128; in intel_emit_post_sync_nonzero_flush()
221 u32 scratch_addr = pc->gtt_offset + 128; in gen6_render_ring_flush()
293 u32 scratch_addr = pc->gtt_offset + 128; in gen7_render_ring_flush()
406 I915_WRITE_START(ring, obj->gtt_offset); in init_ring_common()
413 I915_READ_START(ring) == obj->gtt_offset && in init_ring_common()
469 pc->gtt_offset = obj->gtt_offset; in init_pipe_control()
677 u32 scratch_addr = pc->gtt_offset + 128; in pc_render_add_request()
695 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); in pc_render_add_request()
1010 u32 cs_offset = obj->gtt_offset; in i830_dispatch_execbuffer()
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H A Di915_gem.c2770 obj->gtt_offset = 0; in i915_gem_object_unbind()
2806 val |= obj->gtt_offset & 0xfffff000; in sandybridge_write_fence_reg()
2831 val |= obj->gtt_offset & 0xfffff000; in i965_write_fence_reg()
2856 (obj->gtt_offset & (size - 1)), in i915_write_fence_reg()
2869 val = obj->gtt_offset; in i915_write_fence_reg()
2899 (obj->gtt_offset & (size - 1)), in i830_write_fence_reg()
2901 obj->gtt_offset, size); in i830_write_fence_reg()
2906 val = obj->gtt_offset; in i830_write_fence_reg()
3284 obj->gtt_offset = node->start; in i915_gem_object_bind_to_gtt()
3777 obj->gtt_offset, alignment, in i915_gem_object_pin()
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H A Dintel_fb.c103 info->fb_pbase = dev_priv->mm.gtt_base_addr + obj->gtt_offset; in intelfb_create()
123 obj->gtt_offset, obj); in intelfb_create()
H A Dintel_overlay.c202 overlay->reg_bo->gtt_offset, PAGE_SIZE, in intel_overlay_map_regs()
749 iowrite32(new_bo->gtt_offset + params->offset_Y, &regs->OBUF_0Y); in intel_overlay_do_put_image()
763 iowrite32(new_bo->gtt_offset + params->offset_U, &regs->OBUF_0U); in intel_overlay_do_put_image()
764 iowrite32(new_bo->gtt_offset + params->offset_V, &regs->OBUF_0V); in intel_overlay_do_put_image()
1364 overlay->flip_addr = reg_bo->gtt_offset; in intel_setup_overlay()
1456 error->base = overlay->reg_bo->gtt_offset; in intel_overlay_capture_error_state()
H A Di915_gem_execbuffer.c123 target_offset = target_i915_obj->gtt_offset; in i915_gem_execbuffer_relocate_entry()
230 reloc->offset += obj->gtt_offset; in i915_gem_execbuffer_relocate_entry()
387 entry->offset = obj->gtt_offset; in i915_gem_execbuffer_reserve_object()
477 if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) || in i915_gem_execbuffer_reserve()
1098 exec_start = batch_obj->gtt_offset + args->batch_start_offset; in i915_gem_do_execbuffer()
H A Di915_irq.c906 reloc_offset = src->gtt_offset; in i915_error_object_create()
955 dst->gtt_offset = src->gtt_offset; in i915_error_object_create()
1002 err->gtt_offset = obj->gtt_offset; in capture_bo()
1098 if (acthd >= obj->gtt_offset && in i915_error_first_batchbuffer()
1099 acthd < obj->gtt_offset + obj->base.size) in i915_error_first_batchbuffer()
1505 obj->gtt_offset; in i915_pageflip_stall_check()
1508 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset + in i915_pageflip_stall_check()
H A Di915_debug.c127 obj->gtt_offset, (unsigned int)obj->gtt_space->size); in describe_obj()
324 seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset); in i915_gem_pageflip_info()
329 seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset); in i915_gem_pageflip_info()
587 err->gtt_offset, in print_error_buffers()
711 obj->gtt_offset); in i915_error_state()
736 obj->gtt_offset); in i915_error_state()
H A Dintel_sprite.c146 I915_MODIFY_DISPBASE(SPRSURF(pipe), obj->gtt_offset + sprsurf_offset); in ivb_update_plane()
306 I915_MODIFY_DISPBASE(DVSSURF(pipe), obj->gtt_offset + dvssurf_offset); in ilk_update_plane()
H A Di915_gem_context.c367 intel_ring_emit(ring, new_context->obj->gtt_offset | in mi_set_context()
H A Di915_drv.h222 u32 gtt_offset; member
236 u32 gtt_offset; member
1081 uint32_t gtt_offset; member
H A Dintel_display.c2118 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]); in i9xx_update_plane()
2122 obj->gtt_offset + intel_crtc->dspaddr_offset); in i9xx_update_plane()
2126 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset); in i9xx_update_plane()
2208 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]); in ironlake_update_plane()
2211 obj->gtt_offset + intel_crtc->dspaddr_offset); in ironlake_update_plane()
6491 addr = obj->gtt_offset; in intel_crtc_cursor_set()
7212 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); in intel_gen2_queue_flip()
7253 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); in intel_gen3_queue_flip()
7293 (obj->gtt_offset + intel_crtc->dspaddr_offset) | in intel_gen4_queue_flip()
7336 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); in intel_gen6_queue_flip()
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H A Dintel_pm.c223 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID); in ironlake_enable_fbc()
2813 intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset | in ironlake_enable_rc6()
2836 I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN); in ironlake_enable_rc6()
/freebsd-12.1/sys/dev/drm2/
H A Ddrm_agpsupport.c435 uint32_t gtt_offset, in drm_agp_bind_pages() argument
456 ret = agp_bind_memory(mem, gtt_offset / PAGE_SIZE); in drm_agp_bind_pages()
H A DdrmP.h1793 uint32_t gtt_offset,
1844 uint32_t gtt_offset, in drm_agp_bind_pages() argument
/freebsd-12.1/sys/dev/agp/
H A Dagp_i810.c1234 agp_gen4_install_gatt(device_t dev, const vm_size_t gtt_offset) in agp_gen4_install_gatt() argument
1240 gtt_offset, rman_get_size(sc->sc_res[0]) - gtt_offset, in agp_gen4_install_gatt()