Searched refs:getSubRegs (Results 1 – 5 of 5) sorted by relevance
| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.td | 14 class getSubRegs<int size> { 174 def SGPR_64Regs : RegisterTuples<getSubRegs<2>.ret, 179 def SGPR_128Regs : RegisterTuples<getSubRegs<4>.ret, 186 def SGPR_256Regs : RegisterTuples<getSubRegs<8>.ret, 222 def TTMP_64Regs : RegisterTuples<getSubRegs<2>.ret, 293 getSubRegs<size>.ret>; 350 def VGPR_64 : RegisterTuples<getSubRegs<2>.ret, 355 def VGPR_96 : RegisterTuples<getSubRegs<3>.ret, 361 def VGPR_128 : RegisterTuples<getSubRegs<4>.ret, 368 def VGPR_256 : RegisterTuples<getSubRegs<8>.ret, [all …]
|
| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenMux.cpp | 128 void getSubRegs(unsigned Reg, BitVector &SRs) const; 147 void HexagonGenMux::getSubRegs(unsigned Reg, BitVector &SRs) const { in getSubRegs() function in HexagonGenMux 154 getSubRegs(Reg, Set); in expandReg()
|
| /freebsd-12.1/contrib/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.cpp | 1166 for (auto P : Reg.getSubRegs()) { in CodeGenRegBank() 1320 const CodeGenRegister::SubRegMap &SM = R.getSubRegs(); in computeComposites() 1372 const CodeGenRegister::SubRegMap &SRM1 = Reg1.getSubRegs(); in computeComposites() 1380 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs(); in computeComposites() 1704 const CodeGenRegister::SubRegMap &SRM = Reg->getSubRegs(); in normalizeWeight() 2040 const SubRegMap &SubRegs = Register.getSubRegs(); in computeRegUnitLaneMasks() 2046 if (!SubReg->getSubRegs().empty()) in computeRegUnitLaneMasks() 2169 const CodeGenRegister::SubRegMap &SRM = R->getSubRegs(); in inferSubClassWithSubReg() 2227 const CodeGenRegister *Sub = Super->getSubRegs().find(&SubIdx)->second; in inferMatchingSuperRegClass() 2382 const CodeGenRegister::SubRegMap &SRM = Super->getSubRegs(); in computeCoveredRegisters()
|
| H A D | CodeGenRegisters.h | 182 const SubRegMap &getSubRegs() const { in getSubRegs() function
|
| H A D | RegisterInfoEmitter.cpp | 1669 for (std::pair<CodeGenSubRegIndex*,CodeGenRegister*> P : R.getSubRegs()) { in debugDump()
|