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Searched refs:getSubRegClass (Results 1 – 4 of 4) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h164 const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
H A DSIInstrInfo.cpp3389 RC = TRI->getSubRegClass(RC, MO.getSubReg()); in isLegalRegOperand()
4640 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitUnaryOp()
4647 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0); in splitScalar64BitUnaryOp()
4700 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitAddSub()
4701 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0); in splitScalar64BitAddSub()
4764 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
4769 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
4782 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
4871 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0); in splitScalar64BitBCNT()
H A DSIFixSGPRCopies.cpp290 SrcRC = TRI->getSubRegClass(SrcRC, SrcSubReg); in foldVGPRCopyIntoRegSequence()
H A DSIRegisterInfo.cpp1318 const TargetRegisterClass *SIRegisterInfo::getSubRegClass( in getSubRegClass() function in SIRegisterInfo