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Searched refs:getSchedModel (Results 1 – 25 of 25) sorted by relevance

/freebsd-12.1/contrib/llvm/tools/llvm-mca/Views/
H A DRegisterFileStatistics.cpp23 const MCSchedModel &SM = STI.getSchedModel(); in RegisterFileStatistics()
119 assert(STI.getSchedModel().hasExtraProcessorInfo() && in printView()
122 STI.getSchedModel().getExtraProcessorInfo(); in printView()
H A DSchedulerStatistics.cpp23 : SM(STI.getSchedModel()), LQResourceID(0), SQResourceID(0), NumIssued(0), in SchedulerStatistics()
26 IssuedPerCycle(STI.getSchedModel().NumProcResourceKinds, 0), in SchedulerStatistics()
27 Usage(STI.getSchedModel().NumProcResourceKinds, {0, 0, 0}) { in SchedulerStatistics()
H A DResourcePressureView.cpp28 const MCSchedModel &SM = STI.getSchedModel(); in ResourcePressureView()
109 const MCSchedModel &SM = STI.getSchedModel(); in printResourcePressurePerIter()
152 printColumnNames(FOS, STI.getSchedModel()); in printResourcePressurePerInst()
H A DInstructionInfoView.cpp23 const MCSchedModel &SM = STI.getSchedModel(); in printView()
H A DTimelineView.cpp46 const MCSchedModel &SM = STI.getSchedModel(); in onReservedBuffers()
154 STI.getSchedModel().MicroOpBufferSize); in printWaitTimeEntry()
/freebsd-12.1/contrib/llvm/lib/MCA/
H A DInstrBuilder.cpp34 const MCSchedModel &SM = STI.getSchedModel(); in InstrBuilder()
36 computeProcResourceMasks(STI.getSchedModel(), ProcResourceMasks); in InstrBuilder()
43 const MCSchedModel &SM = STI.getSchedModel(); in initializeUsedResources()
237 const MCSchedModel &SM = STI.getSchedModel(); in populateWrites()
498 assert(STI.getSchedModel().hasInstrSchedModel() && in createInstrDescImpl()
504 const MCSchedModel &SM = STI.getSchedModel(); in createInstrDescImpl()
611 unsigned ProcID = STI.getSchedModel().getProcessorID(); in createInstruction()
H A DContext.cpp33 const MCSchedModel &SM = STI.getSchedModel(); in createDefaultPipeline()
/freebsd-12.1/contrib/llvm/tools/llvm-mca/
H A Dllvm-mca.cpp318 if (!PrintInstructionTables && !STI->getSchedModel().isOutOfOrder()) { in main()
324 if (!STI->getSchedModel().hasInstrSchedModel()) { in main()
330 if (STI->getSchedModel().InstrItineraries) in main()
378 const MCSchedModel &SM = STI->getSchedModel(); in main()
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DTargetSubtargetInfo.cpp63 return getSchedModel().PostRAScheduler; in enablePostRAScheduler()
H A DTargetSchedule.cpp66 SchedModel = TSInfo->getSchedModel(); in init()
H A DMachineCombiner.cpp638 SchedModel = STI->getSchedModel(); in runOnMachineFunction()
H A DEarlyIfConversion.cpp806 SchedModel = STI.getSchedModel(); in runOnMachineFunction()
H A DMachineScheduler.cpp2690 SchedModel = DAG->getSchedModel(); in initialize()
3297 SchedModel = DAG->getSchedModel(); in initialize()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonMachineScheduler.cpp254 SchedModel = DAG->getSchedModel(); in initialize()
261 const InstrItineraryData *Itin = DAG->getSchedModel()->getInstrItineraries(); in initialize()
271 Top.ResourceModel = new VLIWResourceModel(STI, DAG->getSchedModel()); in initialize()
272 Bot.ResourceModel = new VLIWResourceModel(STI, DAG->getSchedModel()); in initialize()
/freebsd-12.1/contrib/llvm/include/llvm/MC/
H A DMCSubtargetInfo.h116 const MCSchedModel &getSchedModel() const { return *CPUSchedModel; } in getSchedModel() function
/freebsd-12.1/contrib/llvm/lib/MC/
H A DMCSchedule.cpp92 const MCSchedModel &SM = STI.getSchedModel(); in getReciprocalThroughput()
H A DMCSubtargetInfo.cpp118 InstrItins = InstrItineraryData(getSchedModel(), Stages, OperandCycles, in initInstrItins()
/freebsd-12.1/contrib/llvm/lib/MCA/Stages/
H A DDispatchStage.cpp77 const MCSchedModel &SM = STI.getSchedModel(); in updateRAWDependencies()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DScheduleDAGInstrs.h257 const TargetSchedModel *getSchedModel() const { return &SchedModel; } in getSchedModel() function
H A DBasicTTIImpl.h453 else if (ST->getSchedModel().LoopMicroOpBufferSize > 0) in getUnrollingPreferences()
454 MaxOps = ST->getSchedModel().LoopMicroOpBufferSize; in getUnrollingPreferences()
491 return getST()->getSchedModel().DefaultLoadLatency; in getInstructionLatency()
/freebsd-12.1/contrib/llvm/lib/MC/MCDisassembler/
H A DDisassembler.cpp193 const MCSchedModel SCModel = STI->getSchedModel(); in getLatency()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.cpp403 const InstrItinerary *II = STI.getSchedModel().InstrItineraries; in getUnits()
414 const InstrItinerary *II = STI.getSchedModel().InstrItineraries; in getOtherReservedSlots()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64ConditionalCompares.cpp937 SchedModel = MF.getSubtarget().getSchedModel(); in runOnMachineFunction()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp1202 PredictableSelectIsExpensive = Subtarget->getSchedModel().isOutOfOrder(); in ARMTargetLowering()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp1912 PredictableSelectIsExpensive = Subtarget.getSchedModel().isOutOfOrder(); in X86TargetLowering()