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Searched refs:getSchedClass (Results 1 – 25 of 32) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DTargetSchedule.cpp111 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass()); in getNumMicroOps()
136 unsigned SchedClass = MI->getDesc().getSchedClass(); in resolveSchedClass()
199 unsigned DefClass = DefMI->getDesc().getSchedClass(); in computeOperandLatency()
263 unsigned SCIdx = TII->get(Opcode).getSchedClass(); in computeInstrLatency()
328 unsigned SchedClass = MI->getDesc().getSchedClass(); in computeReciprocalThroughput()
341 unsigned SchedClass = TII->get(Opcode).getSchedClass(); in computeReciprocalThroughput()
H A DScoreboardHazardRecognizer.cpp128 unsigned idx = MCID->getSchedClass(); in getHazardType()
187 unsigned idx = MCID->getSchedClass(); in EmitInstruction()
H A DTargetInstrInfo.cpp1038 unsigned DefClass = get(DefNode->getMachineOpcode()).getSchedClass(); in getOperandLatency()
1041 unsigned UseClass = get(UseNode->getMachineOpcode()).getSchedClass(); in getOperandLatency()
1053 return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass()); in getInstrLatency()
1065 unsigned Class = MI.getDesc().getSchedClass(); in getNumMicroOps()
1099 return ItinData->getStageLatency(MI.getDesc().getSchedClass()); in getInstrLatency()
1109 unsigned DefClass = DefMI.getDesc().getSchedClass(); in hasLowDefLatency()
1121 unsigned DefClass = DefMI.getDesc().getSchedClass(); in getOperandLatency()
1122 unsigned UseClass = UseMI.getDesc().getSchedClass(); in getOperandLatency()
H A DDFAPacketizer.cpp131 unsigned InsnClass = MID->getSchedClass(); in canReserveResources()
141 unsigned InsnClass = MID->getSchedClass(); in reserveResources()
H A DTargetSubtargetInfo.cpp108 getInstrInfo()->get(MCI.getOpcode()).getSchedClass()); in getSchedInfoStr()
H A DMachineCombiner.cpp363 unsigned Idx = TII->get(Opc).getSchedClass(); in instr2instrSC()
/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZHazardRecognizer.cpp48 const MCSchedClassDesc *SC = getSchedClass(SU); in getNumDecoderSlots()
94 const MCSchedClassDesc *SC = getSchedClass(SU); in fitsIntoCurrentGroup()
172 const MCSchedClassDesc *SC = getSchedClass(SU); in dumpSU()
273 const MCSchedClassDesc *SC = getSchedClass(SU); in EmitInstruction()
342 const MCSchedClassDesc *SC = getSchedClass(SU); in groupingCost()
391 const MCSchedClassDesc *SC = getSchedClass(SU); in resourcesCost()
H A DSystemZHazardRecognizer.h122 const MCSchedClassDesc *getSchedClass(SUnit *SU) const { in getSchedClass() function
H A DSystemZMachineScheduler.cpp254 const MCSchedClassDesc *SC = HazardRec->getSchedClass(SU); in releaseTopNode()
/freebsd-12.1/contrib/llvm/lib/MC/
H A DMCSchedule.cpp71 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass(); in computeInstrLatency()
114 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass(); in getReciprocalThroughput()
/freebsd-12.1/contrib/llvm/tools/llvm-mca/Views/
H A DInstructionInfoView.cpp37 unsigned SchedClassID = MCDesc.getSchedClass(); in printView()
/freebsd-12.1/contrib/llvm/lib/MC/MCDisassembler/
H A DDisassembler.cpp177 unsigned SCClass = Desc.getSchedClass(); in getItineraryLatency()
204 unsigned SCClass = Desc.getSchedClass(); in getLatency()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp68 if (!PredMCID || PredMCID->getSchedClass() != PPC::Sched::IIC_SprMTSPR) in isBCTRAfterSet()
92 unsigned IIC = MCID->getSchedClass(); in mustComeFirst()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64StorePairSuppress.cpp86 unsigned SCIdx = TII->get(AArch64::STPDi).getSchedClass(); in shouldAddSTPToBlock()
H A DAArch64SIMDInstrOpt.cpp228 unsigned SCIdx = InstDesc->getSchedClass(); in shouldReplaceInst()
243 IDesc->getSchedClass()); in shouldReplaceInst()
/freebsd-12.1/contrib/llvm/utils/TableGen/
H A DCodeGenSchedule.h537 CodeGenSchedClass &getSchedClass(unsigned Idx) { in getSchedClass() function
541 const CodeGenSchedClass &getSchedClass(unsigned Idx) const { in getSchedClass() function
H A DSubtargetEmitter.cpp573 ", // " << j << " " << SchedModels.getSchedClass(j).Name << "\n"; in EmitItineraries()
1287 assert(SchedModels.getSchedClass(0).Name == "NoInstrModel" in EmitSchedClassTables()
1295 const CodeGenSchedClass &SchedClass = SchedModels.getSchedClass(SCIdx); in EmitSchedClassTables()
1582 const CodeGenSchedClass &SC = SchedModels.getSchedClass(VC); in emitSchedModelHelpersImpl()
1618 emitPredicates(T, SchedModels.getSchedClass(T.ToClassIdx), PE, OS); in emitSchedModelHelpersImpl()
H A DCodeGenSchedule.cpp915 CodeGenSchedClass &SC = getSchedClass(SCIdx); in collectSchedClasses()
1672 SchedModels.getSchedClass(FromClassIdx) in inferFromTransitions()
1946 const CodeGenSchedClass &SC = getSchedClass(SCIdx); in checkCompleteness()
/freebsd-12.1/contrib/llvm/include/llvm/MC/
H A DMCInstrDesc.h577 unsigned getSchedClass() const { return SchedClass; } in getSchedClass() function
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DScheduleDAGInstrs.h260 const MCSchedClassDesc *getSchedClass(SUnit *SU) const { in getSchedClass() function
/freebsd-12.1/contrib/llvm/lib/MCA/
H A DInstrBuilder.cpp507 unsigned SchedClassID = MCDesc.getSchedClass(); in createInstrDescImpl()
575 SchedClassID = MCDesc.getSchedClass(); in createInstrDescImpl()
/freebsd-12.1/contrib/llvm/include/llvm/MCA/
H A DInstruction.h239 unsigned getSchedClass() const { return RD->SchedClassID; } in getSchedClass() function
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp2109 unsigned SchedClass = MI.getDesc().getSchedClass(); in isEarlySourceInstr()
2301 unsigned SchedClass = MI.getDesc().getSchedClass(); in isLateResultInstr()
2550 unsigned SchedClass = MI.getDesc().getSchedClass(); in isTC1()
2555 unsigned SchedClass = MI.getDesc().getSchedClass(); in isTC2()
2560 unsigned SchedClass = MI.getDesc().getSchedClass(); in isTC2Early()
2565 unsigned SchedClass = MI.getDesc().getSchedClass(); in isTC4x()
4039 return ItinData->getStageLatency(MI.getDesc().getSchedClass()); in getInstrTimingClassLatency()
4289 const InstrStage &IS = *II.beginStage(MI.getDesc().getSchedClass()); in getUnits()
4356 << " Class: " << NewMI->getDesc().getSchedClass()); in genAllInsnTimingClasses()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.cpp404 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass(); in getUnits()
415 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass(); in getOtherReservedSlots()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp3133 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass()); in getNumMicroOpsSwiftLdSt()
3431 unsigned Class = Desc.getSchedClass(); in getNumMicroOps()
3705 unsigned DefClass = DefMCID.getSchedClass(); in getOperandLatency()
3706 unsigned UseClass = UseMCID.getSchedClass(); in getOperandLatency()
4156 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx); in getOperandLatency()
4448 unsigned Class = MCID.getSchedClass(); in getInstrLatency()
4478 return ItinData->getStageLatency(get(Opcode).getSchedClass()); in getInstrLatency()
4515 unsigned DefClass = DefMI.getDesc().getSchedClass(); in hasLowDefLatency()

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