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Searched refs:getOpRegClass (Results 1 – 5 of 5) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DSIAddIMGInit.cpp128 RI->getRegSizeInBits(*TII->getOpRegClass(MI, DstIdx)) / 32; in runOnMachineFunction()
134 MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx)); in runOnMachineFunction()
152 MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx)); in runOnMachineFunction()
H A DSIInstrInfo.h733 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
763 return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8; in getOpSize()
H A DSIInstrInfo.cpp303 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, 0)) / 16; in getMemOperandWithOffset()
307 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, Data0Idx)) / 8; in getMemOperandWithOffset()
3011 const TargetRegisterClass *DstRC = getOpRegClass(MI, DstIdx); in verifyInstruction()
3260 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI, in getOpRegClass() function in SIInstrInfo
3283 return RI.hasVGPRs(getOpRegClass(MI, 0)); in canReadVGPR()
3285 return RI.hasVGPRs(getOpRegClass(MI, OpNo)); in canReadVGPR()
3925 if (VRC || !RI.isSGPRClass(getOpRegClass(MI, 0))) { in legalizeOperands()
3956 const TargetRegisterClass *DstRC = getOpRegClass(MI, 0); in legalizeOperands()
5049 const TargetRegisterClass *NewDstRC = getOpRegClass(Inst, 0); in getDestEquivalentVGPRClass()
H A DSIFixSGPRCopies.cpp685 if (TRI->hasVGPRs(TII->getOpRegClass(MI, 0)) || in runOnMachineFunction()
H A DSIInsertWaitcnts.cpp484 const TargetRegisterClass *RC = TII->getOpRegClass(MIA, OpNo); in getRegInterval()