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Searched refs:getNumDefs (Results 1 – 25 of 49) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/Target/WebAssembly/
H A DWebAssemblyCallIndirectFixup.cpp127 make_range(MI.operands_begin() + MI.getDesc().getNumDefs() + 1, in runOnMachineFunction()
130 Ops.push_back(MI.getOperand(MI.getDesc().getNumDefs())); in runOnMachineFunction()
133 while (MI.getNumOperands() > MI.getDesc().getNumDefs()) in runOnMachineFunction()
H A DWebAssemblyExplicitLocals.cpp272 assert(MI.getDesc().getNumDefs() <= 1); in runOnMachineFunction()
273 if (MI.getDesc().getNumDefs() == 1) { in runOnMachineFunction()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCChecker.cpp94 for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i) in init()
130 for (unsigned i = 0; i < MCID.getNumDefs(); ++i) { in init()
184 for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i) in init()
498 unsigned Defs = HexagonMCInstrInfo::getDesc(MCII, Inst).getNumDefs(); in checkRegistersReadOnly()
515 for (unsigned j = HexagonMCInstrInfo::getDesc(MCII, I).getNumDefs(), in registerUsed()
533 for (unsigned J = 0, N = Desc.getNumDefs(); J < N; ++J) in registerProducer()
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DExecutionDomainFix.cpp239 e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs(); in processDefs()
259 for (unsigned i = mi->getDesc().getNumDefs(), in visitHardInstr()
271 for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) { in visitHardInstr()
290 for (unsigned i = mi->getDesc().getNumDefs(), in visitSoftInstr()
H A DPeepholeOptimizer.cpp870 NumDefs = MI.getDesc().getNumDefs(); in UncoalescableRewriter()
1170 assert(MI.getDesc().getNumDefs() == 1 && in optimizeCoalescableCopy()
1316 if (MCID.getNumDefs() != 1) in isLoadFoldable()
1338 if (MCID.getNumDefs() != 1) in isMoveImmediate()
1520 if (MI.getDesc().getNumDefs() != 1) in findTargetRecurrence()
1759 for (unsigned i = MIDesc.getNumDefs(); i != MI->getNumOperands(); in runOnMachineFunction()
1833 if (Def->getDesc().getNumDefs() != 1) in getNextSourceFromBitcast()
2049 (DefIdx < Def->getDesc().getNumDefs() || in getNextSourceImpl()
H A DReachingDefAnalysis.cpp103 e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs(); in processDefs()
H A DDetectDeadLanes.cpp282 if (MI.getDesc().getNumDefs() != 1) in transferDefinedLanesStep()
430 assert(UseMI.getDesc().getNumDefs() == 1); in determineInitialUsedLanes()
H A DBreakFalseDeps.cpp195 e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs(); in processDefs()
H A DLiveRangeEdit.cpp292 MI->getDesc().getNumDefs() == 1) { in eliminateDeadDef()
H A DImplicitNullChecks.cpp618 unsigned NumDefs = MI->getDesc().getNumDefs(); in insertFaultingInstr()
H A DTargetInstrInfo.cpp152 bool HasDef = MCID.getNumDefs(); in commuteInstructionImpl()
289 unsigned CommutableOpIdx1 = MCID.getNumDefs(); in findCommutedOpIndices()
H A DMachineCSE.cpp572 unsigned NumDefs = MI->getNumDefs(); in ProcessBlock()
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp2046 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_r()
2048 if (II.getNumDefs() >= 1) in fastEmitInst_r()
2068 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rr()
2071 if (II.getNumDefs() >= 1) in fastEmitInst_rr()
2093 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rrr()
2097 if (II.getNumDefs() >= 1) in fastEmitInst_rrr()
2121 if (II.getNumDefs() >= 1) in fastEmitInst_ri()
2144 if (II.getNumDefs() >= 1) in fastEmitInst_rii()
2167 if (II.getNumDefs() >= 1) in fastEmitInst_f()
2189 if (II.getNumDefs() >= 1) in fastEmitInst_rri()
[all …]
H A DScheduleDAGSDNodes.cpp128 if (ResNo >= II.getNumDefs() && in CheckForPhysRegDependency()
129 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) in CheckForPhysRegDependency()
450 if (NumUsed > TII->get(N->getMachineOpcode()).getNumDefs()) in AddSchedEdges()
549 unsigned NRegDefs = SchedDAG->TII->get(Node->getMachineOpcode()).getNumDefs(); in InitNodeNumDefs()
636 OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs(); in computeOperandLatency()
H A DScheduleDAGRRList.cpp1274 NumRes = MCID.getNumDefs(); in getPhysicalRegisterVT()
1406 for (unsigned i = 0; i < MCID.getNumDefs(); ++i) in DelayForLiveRegsBottomUp()
2097 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); in MayReduceRegPressure()
2143 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); in RegPressureDiff()
2272 unsigned NumDefs = TII->get(PN->getMachineOpcode()).getNumDefs(); in unscheduledNode()
2289 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); in unscheduledNode()
2803 unsigned NumRes = MCID.getNumDefs(); in canClobber()
2860 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); in canClobberPhysRegDefs()
3025 unsigned NumRes = MCID.getNumDefs(); in AddPseudoTwoAddrDeps()
H A DInstrEmitter.cpp135 if (i+II.getNumDefs() < II.getNumOperands()) { in EmitCopyFromReg()
137 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF)); in EmitCopyFromReg()
217 for (unsigned i = 0; i < II.getNumDefs(); ++i) { in CreateVirtualRegisters()
831 unsigned NumDefs = II.getNumDefs(); in EmitMachineNode()
H A DResourcePriorityQueue.cpp542 NodeNumDefs = std::min(N->getNumValues(), TID.getNumDefs()); in initNumRegDefsLeft()
/freebsd-12.1/contrib/llvm/lib/MCA/
H A DInstrBuilder.cpp208 unsigned NumExplicitDefs = MCDesc.getNumDefs(); in verifyOperands()
282 unsigned NumExplicitDefs = MCDesc.getNumDefs(); in populateWrites()
407 unsigned NumExplicitUses = MCDesc.getNumOperands() - MCDesc.getNumDefs(); in populateReads()
416 for (unsigned I = 0, OpIndex = MCDesc.getNumDefs(); I < NumExplicitUses; in populateReads()
/freebsd-12.1/contrib/llvm/lib/Target/WebAssembly/InstPrinter/
H A DWebAssemblyInstPrinter.cpp225 else if (OpNo >= MII.get(MI->getOpcode()).getNumDefs()) in printOperand()
232 if (OpNo < MII.get(MI->getOpcode()).getNumDefs()) in printOperand()
/freebsd-12.1/contrib/llvm/lib/CodeGen/GlobalISel/
H A DLocalizer.cpp82 assert(MI.getDesc().getNumDefs() == 1 && in runOnMachineFunction()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64DeadRegisterDefinitionsPass.cpp158 for (int I = 0, E = Desc.getNumDefs(); I != E; ++I) { in processMachineBasicBlock()
H A DAArch64FastISel.cpp1311 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rr()
1312 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rr()
1356 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_ri()
1398 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rs()
1399 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rs()
1443 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rx()
2138 SrcReg = constrainOperandRegClass(II, SrcReg, II.getNumDefs()); in emitStore()
2375 SrcReg = constrainOperandRegClass(II, SrcReg, II.getNumDefs()); in emitCompareAndBranch()
2507 = constrainOperandRegClass(II, CondReg, II.getNumDefs()); in selectBranch()
2525 AddrReg = constrainOperandRegClass(II, AddrReg, II.getNumDefs()); in selectIndirectBr()
[all …]
/freebsd-12.1/contrib/llvm/include/llvm/MC/
H A DMCInstrDesc.h226 unsigned getNumDefs() const { return NumDefs; } in getNumDefs() function
/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZHazardRecognizer.cpp127 if (OpIdx >= MID.getNumDefs() && in has4RegOps()
/freebsd-12.1/contrib/llvm/lib/Target/X86/MCTargetDesc/
H A DX86BaseInfo.h659 unsigned NumDefs = Desc.getNumDefs(); in getOperandBias()

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