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Searched refs:getImplicitDefs (Results 1 – 14 of 14) sorted by relevance

/freebsd-12.1/contrib/llvm/include/llvm/MC/
H A DMCInstrDesc.h546 const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; } in getImplicitDefs() function
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGFast.cpp436 for (const MCPhysReg *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) { in getPhysicalRegisterVT()
514 for (const MCPhysReg *Reg = MCID.getImplicitDefs(); *Reg; ++Reg) { in DelayForLiveRegsBottomUp()
H A DInstrEmitter.cpp850 bool HasPhysRegOuts = NumResults > NumDefs && II.getImplicitDefs()!=nullptr; in EmitMachineNode()
950 unsigned Reg = II.getImplicitDefs()[i - NumDefs]; in EmitMachineNode()
985 if (!UsedRegs.empty() || II.getImplicitDefs() || II.hasOptionalDef()) in EmitMachineNode()
H A DScheduleDAGRRList.cpp1275 for (const MCPhysReg *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) { in getPhysicalRegisterVT()
1415 for (const MCPhysReg *Reg = MCID.getImplicitDefs(); *Reg; ++Reg) in DelayForLiveRegsBottomUp()
2825 = TII->get(SU->getNode()->getMachineOpcode()).getImplicitDefs(); in canClobberReachingPhysRegUse()
2861 const MCPhysReg *ImpDefs = TII->get(N->getMachineOpcode()).getImplicitDefs(); in canClobberPhysRegDefs()
2868 TII->get(SUNode->getMachineOpcode()).getImplicitDefs(); in canClobberPhysRegDefs()
H A DScheduleDAGSDNodes.cpp445 TII->get(N->getMachineOpcode()).getImplicitDefs()) { in AddSchedEdges()
/freebsd-12.1/contrib/llvm/lib/MCA/
H A DInstrBuilder.cpp330 Write.RegisterID = MCDesc.getImplicitDefs()[CurrentDef]; in populateWrites()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCChecker.cpp101 if (const MCPhysReg *ImpDef = MCID.getImplicitDefs()) in init()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DRDFGraph.cpp647 if (!D.getImplicitDefs() && !D.getImplicitUses()) in isFixedReg()
656 const MCPhysReg *ImpR = Op.isDef() ? D.getImplicitDefs() in isFixedReg()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DThumb2SizeReduction.cpp256 for (const MCPhysReg *Regs = MCID.getImplicitDefs(); *Regs; ++Regs) in HasImplicitCPSRDef()
/freebsd-12.1/contrib/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp441 const MCPhysReg Reg = Desc.getImplicitDefs()[I]; in clearsSuperRegisters()
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DMachineInstr.cpp104 for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; in addImplicitDefUseOperands()
/freebsd-12.1/contrib/llvm/lib/CodeGen/MIRParser/
H A DMIParser.cpp947 for (const MCPhysReg *ImpDefs = MCID.getImplicitDefs(); *ImpDefs; ++ImpDefs) in verifyImplicitOperands()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1962 for (const MCPhysReg *ImpDefs = NewDesc.getImplicitDefs(); in optimizeCompareInstr()
/freebsd-12.1/contrib/llvm/lib/MC/MCParser/
H A DAsmParser.cpp5710 ArrayRef<MCPhysReg> ImpDefs(Desc.getImplicitDefs(), in parseMSInlineAsm()