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Searched refs:getAllocatableSet (Results 1 – 10 of 10) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DSIFormMemoryClauses.cpp310 MaxVGPRs = TRI->getAllocatableSet(MF, &AMDGPU::VGPR_32RegClass).count(); in runOnMachineFunction()
311 MaxSGPRs = TRI->getAllocatableSet(MF, &AMDGPU::SGPR_32RegClass).count(); in runOnMachineFunction()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsDelaySlotFiller.cpp337 assert(MF.getSubtarget().getRegisterInfo()->getAllocatableSet(MF).test(R) && in addLiveInRegs()
393 BitVector AllocSet = TRI.getAllocatableSet(MF); in setUnallocatableRegs()
H A DMips16InstrInfo.cpp356 RI.getAllocatableSet in loadImmediate()
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DAggressiveAntiDepBreaker.cpp135 BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]); in AggressiveAntiDepBreaker()
537 BitVector RCBV = TRI->getAllocatableSet(MF, RC); in GetRenameRegisters()
H A DTargetRegisterInfo.cpp218 BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF, in getAllocatableSet() function in TargetRegisterInfo
H A DRegisterScavenging.cpp541 BitVector Candidates = TRI->getAllocatableSet(MF, RC); in scavengeRegister()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DThumb1FrameLowering.cpp613 TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::tGPRRegClassID)); in emitPopSpecialFixUp()
624 TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::hGPRRegClassID)); in emitPopSpecialFixUp()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h365 BitVector getAllocatableSet(const MachineFunction &MF,
/freebsd-12.1/contrib/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp872 TRI->getAllocatableSet in scavengeGPR8()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp1991 BitVector BVAllocatable = TRI->getAllocatableSet(MF); in assignCalleeSavedSpillSlots()