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Searched refs:ctl_reg (Results 1 – 6 of 6) sorted by relevance

/freebsd-12.1/sys/dev/wbwd/
H A Dwbwd.c112 uint8_t ctl_reg; member
371 sc->reg_1 = read_reg(sc, sc->ctl_reg); in sysctl_wb_debug_current()
711 sc->ctl_reg = 0xf5; in wb_probe_enable()
716 sc->ctl_reg = 0xf3; in wb_probe_enable()
719 sc->ctl_reg = 0xf0; in wb_probe_enable()
803 t = read_reg(sc, sc->ctl_reg); in wb_attach()
806 write_reg(sc, sc->ctl_reg, t); in wb_attach()
832 t = read_reg(sc, sc->ctl_reg); in wb_attach()
835 write_reg(sc, sc->ctl_reg, t); in wb_attach()
842 sc->reg_1 = read_reg(sc, sc->ctl_reg); in wb_attach()
[all …]
/freebsd-12.1/sys/dev/drm2/i915/
H A Dintel_lvds.c104 u32 ctl_reg, lvds_reg, stat_reg; in intel_enable_lvds() local
107 ctl_reg = PCH_PP_CONTROL; in intel_enable_lvds()
111 ctl_reg = PP_CONTROL; in intel_enable_lvds()
134 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); in intel_enable_lvds()
147 u32 ctl_reg, lvds_reg, stat_reg; in intel_disable_lvds() local
150 ctl_reg = PCH_PP_CONTROL; in intel_disable_lvds()
154 ctl_reg = PP_CONTROL; in intel_disable_lvds()
161 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON); in intel_disable_lvds()
H A Dintel_hdmi.c298 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe); in hsw_write_infoframe() local
301 u32 val = I915_READ(ctl_reg); in hsw_write_infoframe()
307 I915_WRITE(ctl_reg, val); in hsw_write_infoframe()
320 I915_WRITE(ctl_reg, val); in hsw_write_infoframe()
321 POSTING_READ(ctl_reg); in hsw_write_infoframe()
/freebsd-12.1/sys/amd64/vmm/intel/
H A Dvmx_msr.c81 vmx_set_ctlreg(int ctl_reg, int true_ctl_reg, uint32_t ones_mask, in vmx_set_ctlreg() argument
94 val = rdmsr(ctl_reg); in vmx_set_ctlreg()
106 "truectl 0x%0x\n", i, ctl_reg, true_ctl_reg)); in vmx_set_ctlreg()
130 "0x%0x and true msr 0x%0x", i, ctl_reg, in vmx_set_ctlreg()
H A Dvmx_msr.h45 int vmx_set_ctlreg(int ctl_reg, int true_ctl_reg, uint32_t ones_mask,
/freebsd-12.1/sys/dev/cxgbe/common/
H A Dt4_hw.c346 u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL); in t4_wr_mbox_meat_timeout() local
363 ctl_reg = VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL); in t4_wr_mbox_meat_timeout()
378 ctl = t4_read_reg(adap, ctl_reg); in t4_wr_mbox_meat_timeout()
429 t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW)); in t4_wr_mbox_meat_timeout()
461 v = t4_read_reg(adap, ctl_reg); in t4_wr_mbox_meat_timeout()
466 t4_write_reg(adap, ctl_reg, in t4_wr_mbox_meat_timeout()
476 t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE)); in t4_wr_mbox_meat_timeout()