1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 1999 Jason L. Wright ([email protected])
5 * Copyright (c) 2004 Pyun YongHyeon
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
19 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
20 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
21 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
22 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
23 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
25 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
26 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Effort sponsored in part by the Defense Advanced Research Projects
30 * Agency (DARPA) and Air Force Research Laboratory, Air Force
31 * Materiel Command, USAF, under agreement number F30602-01-2-0537.
32 *
33 * from: OpenBSD: cs4231.c,v 1.21 2003/07/03 20:36:07 jason Exp
34 */
35
36 /*
37 * Driver for CS4231 based audio found in some sun4m systems (cs4231)
38 * based on ideas from the S/Linux project and the NetBSD project.
39 */
40
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
43
44 #include <sys/param.h>
45 #include <sys/systm.h>
46 #include <sys/bus.h>
47 #include <sys/kernel.h>
48 #include <sys/resource.h>
49
50 #include <dev/ofw/ofw_bus.h>
51 #include <dev/ofw/openfirm.h>
52 #include <machine/bus.h>
53 #include <machine/ofw_machdep.h>
54
55 #ifdef HAVE_KERNEL_OPTION_HEADERS
56 #include "opt_snd.h"
57 #endif
58
59 #include <dev/sound/pcm/sound.h>
60 #include <dev/sound/sbus/apcdmareg.h>
61 #include <dev/sound/sbus/cs4231.h>
62
63 #include <sparc64/sbus/sbusvar.h>
64 #include <sparc64/ebus/ebusreg.h>
65
66 #include "mixer_if.h"
67
68 /*
69 * The driver supports CS4231A audio chips found on Sbus/Ebus based
70 * UltraSPARCs. Though, CS4231A says it supports full-duplex mode, I
71 * doubt it due to the lack of independent sampling frequency register
72 * for playback/capture.
73 * Since I couldn't find any documentation for APCDMA programming
74 * information, I guessed the usage of APCDMA from that of OpenBSD's
75 * driver. The EBDMA information of PCIO can be obtained from
76 * http://solutions.sun.com/embedded/databook/web/microprocessors/pcio.html
77 * And CS4231A datasheet can also be obtained from
78 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/4231a.pdf
79 *
80 * Audio capture(recording) was not tested at all and may have bugs.
81 * Sorry, I don't have microphone. Don't try to use full-duplex mode.
82 * It wouldn't work.
83 */
84 #define CS_TIMEOUT 90000
85
86 #define CS4231_MIN_BUF_SZ (16*1024)
87 #define CS4231_DEFAULT_BUF_SZ (32*1024)
88 #define CS4231_MAX_BUF_SZ (64*1024)
89 #define CS4231_MAX_BLK_SZ (8*1024)
90 #define CS4231_MAX_APC_DMA_SZ (8*1024)
91
92
93 #undef CS4231_DEBUG
94 #ifdef CS4231_DEBUG
95 #define DPRINTF(x) printf x
96 #else
97 #define DPRINTF(x)
98 #endif
99 #define CS4231_AUTO_CALIBRATION
100
101 struct cs4231_softc;
102
103 struct cs4231_channel {
104 struct cs4231_softc *parent;
105 struct pcm_channel *channel;
106 struct snd_dbuf *buffer;
107 u_int32_t format;
108 u_int32_t speed;
109 u_int32_t nextaddr;
110 u_int32_t togo;
111 int dir;
112 int locked;
113 };
114
115 #define CS4231_RES_MEM_MAX 4
116 #define CS4231_RES_IRQ_MAX 2
117 struct cs4231_softc {
118 device_t sc_dev;
119 int sc_rid[CS4231_RES_MEM_MAX];
120 struct resource *sc_res[CS4231_RES_MEM_MAX];
121 bus_space_handle_t sc_regh[CS4231_RES_MEM_MAX];
122 bus_space_tag_t sc_regt[CS4231_RES_MEM_MAX];
123
124 int sc_irqrid[CS4231_RES_IRQ_MAX];
125 struct resource *sc_irqres[CS4231_RES_IRQ_MAX];
126 void *sc_ih[CS4231_RES_IRQ_MAX];
127 bus_dma_tag_t sc_dmat[CS4231_RES_IRQ_MAX];
128 int sc_burst;
129
130 u_int32_t sc_bufsz;
131 struct cs4231_channel sc_pch;
132 struct cs4231_channel sc_rch;
133 int sc_enabled;
134 int sc_nmres;
135 int sc_nires;
136 int sc_codecv;
137 int sc_chipvid;
138 int sc_flags;
139 #define CS4231_SBUS 0x01
140 #define CS4231_EBUS 0x02
141
142 struct mtx *sc_lock;
143 };
144
145 struct mix_table {
146 u_int32_t reg:8;
147 u_int32_t bits:8;
148 u_int32_t mute:8;
149 u_int32_t shift:4;
150 u_int32_t neg:1;
151 u_int32_t avail:1;
152 u_int32_t recdev:1;
153 };
154
155 static int cs4231_bus_probe(device_t);
156 static int cs4231_sbus_attach(device_t);
157 static int cs4231_ebus_attach(device_t);
158 static int cs4231_attach_common(struct cs4231_softc *);
159 static int cs4231_bus_detach(device_t);
160 static int cs4231_bus_suspend(device_t);
161 static int cs4231_bus_resume(device_t);
162 static void cs4231_getversion(struct cs4231_softc *);
163 static void cs4231_free_resource(struct cs4231_softc *);
164 static void cs4231_ebdma_reset(struct cs4231_softc *);
165 static void cs4231_power_reset(struct cs4231_softc *, int);
166 static int cs4231_enable(struct cs4231_softc *, int);
167 static void cs4231_disable(struct cs4231_softc *);
168 static void cs4231_write(struct cs4231_softc *, u_int8_t, u_int8_t);
169 static u_int8_t cs4231_read(struct cs4231_softc *, u_int8_t);
170 static void cs4231_sbus_intr(void *);
171 static void cs4231_ebus_pintr(void *arg);
172 static void cs4231_ebus_cintr(void *arg);
173 static int cs4231_mixer_init(struct snd_mixer *);
174 static void cs4231_mixer_set_value(struct cs4231_softc *,
175 const struct mix_table *, u_int8_t);
176 static int cs4231_mixer_set(struct snd_mixer *, u_int32_t, u_int32_t,
177 u_int32_t);
178 static u_int32_t cs4231_mixer_setrecsrc(struct snd_mixer *, u_int32_t);
179 static void *cs4231_chan_init(kobj_t, void *, struct snd_dbuf *,
180 struct pcm_channel *, int);
181 static int cs4231_chan_setformat(kobj_t, void *, u_int32_t);
182 static u_int32_t cs4231_chan_setspeed(kobj_t, void *, u_int32_t);
183 static void cs4231_chan_fs(struct cs4231_softc *, int, u_int8_t);
184 static u_int32_t cs4231_chan_setblocksize(kobj_t, void *, u_int32_t);
185 static int cs4231_chan_trigger(kobj_t, void *, int);
186 static u_int32_t cs4231_chan_getptr(kobj_t, void *);
187 static struct pcmchan_caps *
188 cs4231_chan_getcaps(kobj_t, void *);
189 static void cs4231_trigger(struct cs4231_channel *);
190 static void cs4231_apcdma_trigger(struct cs4231_softc *,
191 struct cs4231_channel *);
192 static void cs4231_ebdma_trigger(struct cs4231_softc *,
193 struct cs4231_channel *);
194 static void cs4231_halt(struct cs4231_channel *);
195
196 #define CS4231_LOCK(sc) snd_mtxlock(sc->sc_lock)
197 #define CS4231_UNLOCK(sc) snd_mtxunlock(sc->sc_lock)
198 #define CS4231_LOCK_ASSERT(sc) snd_mtxassert(sc->sc_lock)
199
200 #define CS_WRITE(sc,r,v) \
201 bus_space_write_1((sc)->sc_regt[0], (sc)->sc_regh[0], (r) << 2, (v))
202 #define CS_READ(sc,r) \
203 bus_space_read_1((sc)->sc_regt[0], (sc)->sc_regh[0], (r) << 2)
204
205 #define APC_WRITE(sc,r,v) \
206 bus_space_write_4(sc->sc_regt[0], sc->sc_regh[0], r, v)
207 #define APC_READ(sc,r) \
208 bus_space_read_4(sc->sc_regt[0], sc->sc_regh[0], r)
209
210 #define EBDMA_P_WRITE(sc,r,v) \
211 bus_space_write_4((sc)->sc_regt[1], (sc)->sc_regh[1], (r), (v))
212 #define EBDMA_P_READ(sc,r) \
213 bus_space_read_4((sc)->sc_regt[1], (sc)->sc_regh[1], (r))
214
215 #define EBDMA_C_WRITE(sc,r,v) \
216 bus_space_write_4((sc)->sc_regt[2], (sc)->sc_regh[2], (r), (v))
217 #define EBDMA_C_READ(sc,r) \
218 bus_space_read_4((sc)->sc_regt[2], (sc)->sc_regh[2], (r))
219
220 #define AUXIO_CODEC 0x00
221 #define AUXIO_WRITE(sc,r,v) \
222 bus_space_write_4((sc)->sc_regt[3], (sc)->sc_regh[3], (r), (v))
223 #define AUXIO_READ(sc,r) \
224 bus_space_read_4((sc)->sc_regt[3], (sc)->sc_regh[3], (r))
225
226 #define CODEC_WARM_RESET 0
227 #define CODEC_COLD_RESET 1
228
229 /* SBus */
230 static device_method_t cs4231_sbus_methods[] = {
231 DEVMETHOD(device_probe, cs4231_bus_probe),
232 DEVMETHOD(device_attach, cs4231_sbus_attach),
233 DEVMETHOD(device_detach, cs4231_bus_detach),
234 DEVMETHOD(device_suspend, cs4231_bus_suspend),
235 DEVMETHOD(device_resume, cs4231_bus_resume),
236
237 DEVMETHOD_END
238 };
239
240 static driver_t cs4231_sbus_driver = {
241 "pcm",
242 cs4231_sbus_methods,
243 PCM_SOFTC_SIZE
244 };
245
246 DRIVER_MODULE(snd_audiocs, sbus, cs4231_sbus_driver, pcm_devclass, 0, 0);
247
248 /* EBus */
249 static device_method_t cs4231_ebus_methods[] = {
250 DEVMETHOD(device_probe, cs4231_bus_probe),
251 DEVMETHOD(device_attach, cs4231_ebus_attach),
252 DEVMETHOD(device_detach, cs4231_bus_detach),
253 DEVMETHOD(device_suspend, cs4231_bus_suspend),
254 DEVMETHOD(device_resume, cs4231_bus_resume),
255
256 DEVMETHOD_END
257 };
258
259 static driver_t cs4231_ebus_driver = {
260 "pcm",
261 cs4231_ebus_methods,
262 PCM_SOFTC_SIZE
263 };
264
265 DRIVER_MODULE(snd_audiocs, ebus, cs4231_ebus_driver, pcm_devclass, 0, 0);
266 MODULE_DEPEND(snd_audiocs, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
267 MODULE_VERSION(snd_audiocs, 1);
268
269
270 static u_int32_t cs4231_fmt[] = {
271 SND_FORMAT(AFMT_U8, 1, 0),
272 SND_FORMAT(AFMT_U8, 2, 0),
273 SND_FORMAT(AFMT_MU_LAW, 1, 0),
274 SND_FORMAT(AFMT_MU_LAW, 2, 0),
275 SND_FORMAT(AFMT_A_LAW, 1, 0),
276 SND_FORMAT(AFMT_A_LAW, 2, 0),
277 SND_FORMAT(AFMT_IMA_ADPCM, 1, 0),
278 SND_FORMAT(AFMT_IMA_ADPCM, 2, 0),
279 SND_FORMAT(AFMT_S16_LE, 1, 0),
280 SND_FORMAT(AFMT_S16_LE, 2, 0),
281 SND_FORMAT(AFMT_S16_BE, 1, 0),
282 SND_FORMAT(AFMT_S16_BE, 2, 0),
283 0
284 };
285
286 static struct pcmchan_caps cs4231_caps = {5510, 48000, cs4231_fmt, 0};
287
288 /*
289 * sound(4) channel interface
290 */
291 static kobj_method_t cs4231_chan_methods[] = {
292 KOBJMETHOD(channel_init, cs4231_chan_init),
293 KOBJMETHOD(channel_setformat, cs4231_chan_setformat),
294 KOBJMETHOD(channel_setspeed, cs4231_chan_setspeed),
295 KOBJMETHOD(channel_setblocksize, cs4231_chan_setblocksize),
296 KOBJMETHOD(channel_trigger, cs4231_chan_trigger),
297 KOBJMETHOD(channel_getptr, cs4231_chan_getptr),
298 KOBJMETHOD(channel_getcaps, cs4231_chan_getcaps),
299 KOBJMETHOD_END
300 };
301 CHANNEL_DECLARE(cs4231_chan);
302
303 /*
304 * sound(4) mixer interface
305 */
306 static kobj_method_t cs4231_mixer_methods[] = {
307 KOBJMETHOD(mixer_init, cs4231_mixer_init),
308 KOBJMETHOD(mixer_set, cs4231_mixer_set),
309 KOBJMETHOD(mixer_setrecsrc, cs4231_mixer_setrecsrc),
310 KOBJMETHOD_END
311 };
312 MIXER_DECLARE(cs4231_mixer);
313
314 static int
cs4231_bus_probe(device_t dev)315 cs4231_bus_probe(device_t dev)
316 {
317 const char *compat, *name;
318
319 compat = ofw_bus_get_compat(dev);
320 name = ofw_bus_get_name(dev);
321 if (strcmp("SUNW,CS4231", name) == 0 ||
322 (compat != NULL && strcmp("SUNW,CS4231", compat) == 0)) {
323 device_set_desc(dev, "Sun Audiocs");
324 return (BUS_PROBE_DEFAULT);
325 }
326 return (ENXIO);
327 }
328
329 static int
cs4231_sbus_attach(device_t dev)330 cs4231_sbus_attach(device_t dev)
331 {
332 struct cs4231_softc *sc;
333 int burst;
334
335 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
336 sc->sc_dev = dev;
337 /*
338 * XXX
339 * No public documentation exists on programming burst size of APCDMA.
340 */
341 burst = sbus_get_burstsz(sc->sc_dev);
342 if ((burst & SBUS_BURST_64))
343 sc->sc_burst = 64;
344 else if ((burst & SBUS_BURST_32))
345 sc->sc_burst = 32;
346 else if ((burst & SBUS_BURST_16))
347 sc->sc_burst = 16;
348 else
349 sc->sc_burst = 0;
350 sc->sc_flags = CS4231_SBUS;
351 sc->sc_nmres = 1;
352 sc->sc_nires = 1;
353 return cs4231_attach_common(sc);
354 }
355
356 static int
cs4231_ebus_attach(device_t dev)357 cs4231_ebus_attach(device_t dev)
358 {
359 struct cs4231_softc *sc;
360
361 sc = malloc(sizeof(struct cs4231_softc), M_DEVBUF, M_NOWAIT | M_ZERO);
362 if (sc == NULL) {
363 device_printf(dev, "cannot allocate softc\n");
364 return (ENOMEM);
365 }
366 sc->sc_dev = dev;
367 sc->sc_burst = EBDCSR_BURST_1;
368 sc->sc_nmres = CS4231_RES_MEM_MAX;
369 sc->sc_nires = CS4231_RES_IRQ_MAX;
370 sc->sc_flags = CS4231_EBUS;
371 return cs4231_attach_common(sc);
372 }
373
374 static int
cs4231_attach_common(struct cs4231_softc * sc)375 cs4231_attach_common(struct cs4231_softc *sc)
376 {
377 char status[SND_STATUSLEN];
378 driver_intr_t *ihandler;
379 int i;
380
381 sc->sc_lock = snd_mtxcreate(device_get_nameunit(sc->sc_dev),
382 "snd_cs4231 softc");
383
384 for (i = 0; i < sc->sc_nmres; i++) {
385 sc->sc_rid[i] = i;
386 if ((sc->sc_res[i] = bus_alloc_resource_any(sc->sc_dev,
387 SYS_RES_MEMORY, &sc->sc_rid[i], RF_ACTIVE)) == NULL) {
388 device_printf(sc->sc_dev,
389 "cannot map register %d\n", i);
390 goto fail;
391 }
392 sc->sc_regt[i] = rman_get_bustag(sc->sc_res[i]);
393 sc->sc_regh[i] = rman_get_bushandle(sc->sc_res[i]);
394 }
395 for (i = 0; i < sc->sc_nires; i++) {
396 sc->sc_irqrid[i] = i;
397 if ((sc->sc_irqres[i] = bus_alloc_resource_any(sc->sc_dev,
398 SYS_RES_IRQ, &sc->sc_irqrid[i], RF_SHAREABLE | RF_ACTIVE))
399 == NULL) {
400 if ((sc->sc_flags & CS4231_SBUS) != 0)
401 device_printf(sc->sc_dev,
402 "cannot allocate interrupt\n");
403 else
404 device_printf(sc->sc_dev, "cannot allocate %s "
405 "interrupt\n", i == 0 ? "capture" :
406 "playback");
407 goto fail;
408 }
409 }
410
411 ihandler = cs4231_sbus_intr;
412 for (i = 0; i < sc->sc_nires; i++) {
413 if ((sc->sc_flags & CS4231_EBUS) != 0) {
414 if (i == 0)
415 ihandler = cs4231_ebus_cintr;
416 else
417 ihandler = cs4231_ebus_pintr;
418 }
419 if (snd_setup_intr(sc->sc_dev, sc->sc_irqres[i], INTR_MPSAFE,
420 ihandler, sc, &sc->sc_ih[i])) {
421 if ((sc->sc_flags & CS4231_SBUS) != 0)
422 device_printf(sc->sc_dev,
423 "cannot set up interrupt\n");
424 else
425 device_printf(sc->sc_dev, "cannot set up %s "
426 " interrupt\n", i == 0 ? "capture" :
427 "playback");
428 goto fail;
429 }
430 }
431
432 sc->sc_bufsz = pcm_getbuffersize(sc->sc_dev, CS4231_MIN_BUF_SZ,
433 CS4231_DEFAULT_BUF_SZ, CS4231_MAX_BUF_SZ);
434 for (i = 0; i < sc->sc_nires; i++) {
435 if (bus_dma_tag_create(
436 bus_get_dma_tag(sc->sc_dev),/* parent */
437 64, 0, /* alignment, boundary */
438 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
439 BUS_SPACE_MAXADDR, /* highaddr */
440 NULL, NULL, /* filtfunc, filtfuncarg */
441 sc->sc_bufsz, /* maxsize */
442 1, /* nsegments */
443 sc->sc_bufsz, /* maxsegsz */
444 BUS_DMA_ALLOCNOW, /* flags */
445 NULL, /* lockfunc */
446 NULL, /* lockfuncarg */
447 &sc->sc_dmat[i])) {
448 if ((sc->sc_flags & CS4231_SBUS) != 0)
449 device_printf(sc->sc_dev,
450 "cannot allocate DMA tag\n");
451 else
452 device_printf(sc->sc_dev, "cannot allocate %s "
453 "DMA tag\n", i == 0 ? "capture" :
454 "playback");
455 goto fail;
456 }
457 }
458 cs4231_enable(sc, CODEC_WARM_RESET);
459 cs4231_getversion(sc);
460 if (mixer_init(sc->sc_dev, &cs4231_mixer_class, sc) != 0)
461 goto fail;
462 if (pcm_register(sc->sc_dev, sc, 1, 1)) {
463 device_printf(sc->sc_dev, "cannot register to pcm\n");
464 goto fail;
465 }
466 if (pcm_addchan(sc->sc_dev, PCMDIR_REC, &cs4231_chan_class, sc) != 0)
467 goto chan_fail;
468 if (pcm_addchan(sc->sc_dev, PCMDIR_PLAY, &cs4231_chan_class, sc) != 0)
469 goto chan_fail;
470 if ((sc->sc_flags & CS4231_SBUS) != 0)
471 snprintf(status, SND_STATUSLEN, "at mem 0x%lx irq %ld bufsz %u",
472 rman_get_start(sc->sc_res[0]),
473 rman_get_start(sc->sc_irqres[0]), sc->sc_bufsz);
474 else
475 snprintf(status, SND_STATUSLEN, "at io 0x%lx 0x%lx 0x%lx 0x%lx "
476 "irq %ld %ld bufsz %u", rman_get_start(sc->sc_res[0]),
477 rman_get_start(sc->sc_res[1]),
478 rman_get_start(sc->sc_res[2]),
479 rman_get_start(sc->sc_res[3]),
480 rman_get_start(sc->sc_irqres[0]),
481 rman_get_start(sc->sc_irqres[1]), sc->sc_bufsz);
482 pcm_setstatus(sc->sc_dev, status);
483 return (0);
484
485 chan_fail:
486 pcm_unregister(sc->sc_dev);
487 fail:
488 cs4231_free_resource(sc);
489 return (ENXIO);
490 }
491
492 static int
cs4231_bus_detach(device_t dev)493 cs4231_bus_detach(device_t dev)
494 {
495 struct cs4231_softc *sc;
496 struct cs4231_channel *pch, *rch;
497 int error;
498
499 sc = pcm_getdevinfo(dev);
500 CS4231_LOCK(sc);
501 pch = &sc->sc_pch;
502 rch = &sc->sc_pch;
503 if (pch->locked || rch->locked) {
504 CS4231_UNLOCK(sc);
505 return (EBUSY);
506 }
507 /*
508 * Since EBDMA requires valid DMA buffer to drain its FIFO, we need
509 * real DMA buffer for draining.
510 */
511 if ((sc->sc_flags & CS4231_EBUS) != 0)
512 cs4231_ebdma_reset(sc);
513 CS4231_UNLOCK(sc);
514 error = pcm_unregister(dev);
515 if (error)
516 return (error);
517 cs4231_free_resource(sc);
518 return (0);
519 }
520
521 static int
cs4231_bus_suspend(device_t dev)522 cs4231_bus_suspend(device_t dev)
523 {
524
525 return (ENXIO);
526 }
527
528 static int
cs4231_bus_resume(device_t dev)529 cs4231_bus_resume(device_t dev)
530 {
531
532 return (ENXIO);
533 }
534
535 static void
cs4231_getversion(struct cs4231_softc * sc)536 cs4231_getversion(struct cs4231_softc *sc)
537 {
538 u_int8_t v;
539
540 v = cs4231_read(sc, CS_MISC_INFO);
541 sc->sc_codecv = v & CS_CODEC_ID_MASK;
542 v = cs4231_read(sc, CS_VERSION_ID);
543 v &= (CS_VERSION_NUMBER | CS_VERSION_CHIPID);
544 sc->sc_chipvid = v;
545 switch(v) {
546 case 0x80:
547 device_printf(sc->sc_dev, "<CS4231 Codec Id. %d>\n",
548 sc->sc_codecv);
549 break;
550 case 0xa0:
551 device_printf(sc->sc_dev, "<CS4231A Codec Id. %d>\n",
552 sc->sc_codecv);
553 break;
554 case 0x82:
555 device_printf(sc->sc_dev, "<CS4232 Codec Id. %d>\n",
556 sc->sc_codecv);
557 break;
558 default:
559 device_printf(sc->sc_dev,
560 "<Unknown 0x%x Codec Id. %d\n", v, sc->sc_codecv);
561 break;
562 }
563 }
564
565 static void
cs4231_ebdma_reset(struct cs4231_softc * sc)566 cs4231_ebdma_reset(struct cs4231_softc *sc)
567 {
568 int i;
569
570 /* playback */
571 EBDMA_P_WRITE(sc, EBDMA_DCSR,
572 EBDMA_P_READ(sc, EBDMA_DCSR) & ~(EBDCSR_INTEN | EBDCSR_NEXTEN));
573 EBDMA_P_WRITE(sc, EBDMA_DCSR, EBDCSR_RESET);
574 for (i = CS_TIMEOUT;
575 i && EBDMA_P_READ(sc, EBDMA_DCSR) & EBDCSR_DRAIN; i--)
576 DELAY(1);
577 if (i == 0)
578 device_printf(sc->sc_dev,
579 "timeout waiting for playback DMA reset\n");
580 EBDMA_P_WRITE(sc, EBDMA_DCSR, sc->sc_burst);
581 /* capture */
582 EBDMA_C_WRITE(sc, EBDMA_DCSR,
583 EBDMA_C_READ(sc, EBDMA_DCSR) & ~(EBDCSR_INTEN | EBDCSR_NEXTEN));
584 EBDMA_C_WRITE(sc, EBDMA_DCSR, EBDCSR_RESET);
585 for (i = CS_TIMEOUT;
586 i && EBDMA_C_READ(sc, EBDMA_DCSR) & EBDCSR_DRAIN; i--)
587 DELAY(1);
588 if (i == 0)
589 device_printf(sc->sc_dev,
590 "timeout waiting for capture DMA reset\n");
591 EBDMA_C_WRITE(sc, EBDMA_DCSR, sc->sc_burst);
592 }
593
594 static void
cs4231_power_reset(struct cs4231_softc * sc,int how)595 cs4231_power_reset(struct cs4231_softc *sc, int how)
596 {
597 u_int32_t v;
598 int i;
599
600 if ((sc->sc_flags & CS4231_SBUS) != 0) {
601 APC_WRITE(sc, APC_CSR, APC_CSR_RESET);
602 DELAY(10);
603 APC_WRITE(sc, APC_CSR, 0);
604 DELAY(10);
605 APC_WRITE(sc,
606 APC_CSR, APC_READ(sc, APC_CSR) | APC_CSR_CODEC_RESET);
607 DELAY(20);
608 APC_WRITE(sc,
609 APC_CSR, APC_READ(sc, APC_CSR) & (~APC_CSR_CODEC_RESET));
610 } else {
611 v = AUXIO_READ(sc, AUXIO_CODEC);
612 if (how == CODEC_WARM_RESET && v != 0) {
613 AUXIO_WRITE(sc, AUXIO_CODEC, 0);
614 DELAY(20);
615 } else if (how == CODEC_COLD_RESET){
616 AUXIO_WRITE(sc, AUXIO_CODEC, 1);
617 DELAY(20);
618 AUXIO_WRITE(sc, AUXIO_CODEC, 0);
619 DELAY(20);
620 }
621 cs4231_ebdma_reset(sc);
622 }
623
624 for (i = CS_TIMEOUT;
625 i && CS_READ(sc, CS4231_IADDR) == CS_IN_INIT; i--)
626 DELAY(10);
627 if (i == 0)
628 device_printf(sc->sc_dev, "timeout waiting for reset\n");
629
630 /* turn on cs4231 mode */
631 cs4231_write(sc, CS_MISC_INFO,
632 cs4231_read(sc, CS_MISC_INFO) | CS_MODE2);
633 /* enable interrupts & clear CSR */
634 cs4231_write(sc, CS_PIN_CONTROL,
635 cs4231_read(sc, CS_PIN_CONTROL) | INTERRUPT_ENABLE);
636 CS_WRITE(sc, CS4231_STATUS, 0);
637 /* enable DAC output */
638 cs4231_write(sc, CS_LEFT_OUTPUT_CONTROL,
639 cs4231_read(sc, CS_LEFT_OUTPUT_CONTROL) & ~OUTPUT_MUTE);
640 cs4231_write(sc, CS_RIGHT_OUTPUT_CONTROL,
641 cs4231_read(sc, CS_RIGHT_OUTPUT_CONTROL) & ~OUTPUT_MUTE);
642 /* mute AUX1 since it generates noises */
643 cs4231_write(sc, CS_LEFT_AUX1_CONTROL,
644 cs4231_read(sc, CS_LEFT_AUX1_CONTROL) | AUX_INPUT_MUTE);
645 cs4231_write(sc, CS_RIGHT_AUX1_CONTROL,
646 cs4231_read(sc, CS_RIGHT_AUX1_CONTROL) | AUX_INPUT_MUTE);
647 /* protect buffer underrun and set output level to 0dB */
648 cs4231_write(sc, CS_ALT_FEATURE1,
649 cs4231_read(sc, CS_ALT_FEATURE1) | CS_DAC_ZERO | CS_OUTPUT_LVL);
650 /* enable high pass filter, dual xtal was disabled due to noises */
651 cs4231_write(sc, CS_ALT_FEATURE2,
652 cs4231_read(sc, CS_ALT_FEATURE2) | CS_HPF_ENABLE);
653 }
654
655 static int
cs4231_enable(struct cs4231_softc * sc,int how)656 cs4231_enable(struct cs4231_softc *sc, int how)
657 {
658 cs4231_power_reset(sc, how);
659 sc->sc_enabled = 1;
660 return (0);
661 }
662
663 static void
cs4231_disable(struct cs4231_softc * sc)664 cs4231_disable(struct cs4231_softc *sc)
665 {
666 u_int8_t v;
667
668 CS4231_LOCK_ASSERT(sc);
669
670 if (sc->sc_enabled == 0)
671 return;
672 sc->sc_enabled = 0;
673 CS4231_UNLOCK(sc);
674 cs4231_halt(&sc->sc_pch);
675 cs4231_halt(&sc->sc_rch);
676 CS4231_LOCK(sc);
677 v = cs4231_read(sc, CS_PIN_CONTROL) & ~INTERRUPT_ENABLE;
678 cs4231_write(sc, CS_PIN_CONTROL, v);
679
680 if ((sc->sc_flags & CS4231_SBUS) != 0) {
681 APC_WRITE(sc, APC_CSR, APC_CSR_RESET);
682 DELAY(10);
683 APC_WRITE(sc, APC_CSR, 0);
684 DELAY(10);
685 } else
686 cs4231_ebdma_reset(sc);
687 }
688
689 static void
cs4231_free_resource(struct cs4231_softc * sc)690 cs4231_free_resource(struct cs4231_softc *sc)
691 {
692 int i;
693
694 CS4231_LOCK(sc);
695 cs4231_disable(sc);
696 CS4231_UNLOCK(sc);
697 for (i = 0; i < sc->sc_nires; i++) {
698 if (sc->sc_irqres[i]) {
699 if (sc->sc_ih[i]) {
700 bus_teardown_intr(sc->sc_dev, sc->sc_irqres[i],
701 sc->sc_ih[i]);
702 sc->sc_ih[i] = NULL;
703 }
704 bus_release_resource(sc->sc_dev, SYS_RES_IRQ,
705 sc->sc_irqrid[i], sc->sc_irqres[i]);
706 sc->sc_irqres[i] = NULL;
707 }
708 }
709 for (i = 0; i < sc->sc_nires; i++) {
710 if (sc->sc_dmat[i])
711 bus_dma_tag_destroy(sc->sc_dmat[i]);
712 }
713 for (i = 0; i < sc->sc_nmres; i++) {
714 if (sc->sc_res[i])
715 bus_release_resource(sc->sc_dev, SYS_RES_MEMORY,
716 sc->sc_rid[i], sc->sc_res[i]);
717 }
718 snd_mtxfree(sc->sc_lock);
719 free(sc, M_DEVBUF);
720 }
721
722 static void
cs4231_write(struct cs4231_softc * sc,u_int8_t r,u_int8_t v)723 cs4231_write(struct cs4231_softc *sc, u_int8_t r, u_int8_t v)
724 {
725 CS_WRITE(sc, CS4231_IADDR, r);
726 CS_WRITE(sc, CS4231_IDATA, v);
727 }
728
729 static u_int8_t
cs4231_read(struct cs4231_softc * sc,u_int8_t r)730 cs4231_read(struct cs4231_softc *sc, u_int8_t r)
731 {
732 CS_WRITE(sc, CS4231_IADDR, r);
733 return (CS_READ(sc, CS4231_IDATA));
734 }
735
736 static void
cs4231_sbus_intr(void * arg)737 cs4231_sbus_intr(void *arg)
738 {
739 struct cs4231_softc *sc;
740 struct cs4231_channel *pch, *rch;
741 u_int32_t csr;
742 u_int8_t status;
743
744 sc = arg;
745 CS4231_LOCK(sc);
746
747 csr = APC_READ(sc, APC_CSR);
748 if ((csr & APC_CSR_GI) == 0) {
749 CS4231_UNLOCK(sc);
750 return;
751 }
752 APC_WRITE(sc, APC_CSR, csr);
753
754 if ((csr & APC_CSR_EIE) && (csr & APC_CSR_EI)) {
755 status = cs4231_read(sc, CS_TEST_AND_INIT);
756 device_printf(sc->sc_dev,
757 "apc error interrupt : stat = 0x%x\n", status);
758 }
759
760 pch = rch = NULL;
761 if ((csr & APC_CSR_PMIE) && (csr & APC_CSR_PMI)) {
762 u_long nextaddr, saddr;
763 u_int32_t togo;
764
765 pch = &sc->sc_pch;
766 togo = pch->togo;
767 saddr = sndbuf_getbufaddr(pch->buffer);
768 nextaddr = pch->nextaddr + togo;
769 if (nextaddr >= saddr + sndbuf_getsize(pch->buffer))
770 nextaddr = saddr;
771 APC_WRITE(sc, APC_PNVA, nextaddr);
772 APC_WRITE(sc, APC_PNC, togo);
773 pch->nextaddr = nextaddr;
774 }
775
776 if ((csr & APC_CSR_CIE) && (csr & APC_CSR_CI) && (csr & APC_CSR_CD)) {
777 u_long nextaddr, saddr;
778 u_int32_t togo;
779
780 rch = &sc->sc_rch;
781 togo = rch->togo;
782 saddr = sndbuf_getbufaddr(rch->buffer);
783 nextaddr = rch->nextaddr + togo;
784 if (nextaddr >= saddr + sndbuf_getsize(rch->buffer))
785 nextaddr = saddr;
786 APC_WRITE(sc, APC_CNVA, nextaddr);
787 APC_WRITE(sc, APC_CNC, togo);
788 rch->nextaddr = nextaddr;
789 }
790 CS4231_UNLOCK(sc);
791 if (pch)
792 chn_intr(pch->channel);
793 if (rch)
794 chn_intr(rch->channel);
795 }
796
797 /* playback interrupt handler */
798 static void
cs4231_ebus_pintr(void * arg)799 cs4231_ebus_pintr(void *arg)
800 {
801 struct cs4231_softc *sc;
802 struct cs4231_channel *ch;
803 u_int32_t csr;
804 u_int8_t status;
805
806 sc = arg;
807 CS4231_LOCK(sc);
808
809 csr = EBDMA_P_READ(sc, EBDMA_DCSR);
810 if ((csr & EBDCSR_INT) == 0) {
811 CS4231_UNLOCK(sc);
812 return;
813 }
814
815 if ((csr & EBDCSR_ERR)) {
816 status = cs4231_read(sc, CS_TEST_AND_INIT);
817 device_printf(sc->sc_dev,
818 "ebdma error interrupt : stat = 0x%x\n", status);
819 }
820 EBDMA_P_WRITE(sc, EBDMA_DCSR, csr | EBDCSR_TC);
821
822 ch = NULL;
823 if (csr & EBDCSR_TC) {
824 u_long nextaddr, saddr;
825 u_int32_t togo;
826
827 ch = &sc->sc_pch;
828 togo = ch->togo;
829 saddr = sndbuf_getbufaddr(ch->buffer);
830 nextaddr = ch->nextaddr + togo;
831 if (nextaddr >= saddr + sndbuf_getsize(ch->buffer))
832 nextaddr = saddr;
833 /*
834 * EBDMA_DCNT is loaded automatically
835 * EBDMA_P_WRITE(sc, EBDMA_DCNT, togo);
836 */
837 EBDMA_P_WRITE(sc, EBDMA_DADDR, nextaddr);
838 ch->nextaddr = nextaddr;
839 }
840 CS4231_UNLOCK(sc);
841 if (ch)
842 chn_intr(ch->channel);
843 }
844
845 /* capture interrupt handler */
846 static void
cs4231_ebus_cintr(void * arg)847 cs4231_ebus_cintr(void *arg)
848 {
849 struct cs4231_softc *sc;
850 struct cs4231_channel *ch;
851 u_int32_t csr;
852 u_int8_t status;
853
854 sc = arg;
855 CS4231_LOCK(sc);
856
857 csr = EBDMA_C_READ(sc, EBDMA_DCSR);
858 if ((csr & EBDCSR_INT) == 0) {
859 CS4231_UNLOCK(sc);
860 return;
861 }
862 if ((csr & EBDCSR_ERR)) {
863 status = cs4231_read(sc, CS_TEST_AND_INIT);
864 device_printf(sc->sc_dev,
865 "dma error interrupt : stat = 0x%x\n", status);
866 }
867 EBDMA_C_WRITE(sc, EBDMA_DCSR, csr | EBDCSR_TC);
868
869 ch = NULL;
870 if (csr & EBDCSR_TC) {
871 u_long nextaddr, saddr;
872 u_int32_t togo;
873
874 ch = &sc->sc_rch;
875 togo = ch->togo;
876 saddr = sndbuf_getbufaddr(ch->buffer);
877 nextaddr = ch->nextaddr + togo;
878 if (nextaddr >= saddr + sndbuf_getblksz(ch->buffer))
879 nextaddr = saddr;
880 /*
881 * EBDMA_DCNT is loaded automatically
882 * EBDMA_C_WRITE(sc, EBDMA_DCNT, togo);
883 */
884 EBDMA_C_WRITE(sc, EBDMA_DADDR, nextaddr);
885 ch->nextaddr = nextaddr;
886 }
887 CS4231_UNLOCK(sc);
888 if (ch)
889 chn_intr(ch->channel);
890 }
891
892 static const struct mix_table cs4231_mix_table[SOUND_MIXER_NRDEVICES][2] = {
893 [SOUND_MIXER_PCM] = {
894 { CS_LEFT_OUTPUT_CONTROL, 6, OUTPUT_MUTE, 0, 1, 1, 0 },
895 { CS_RIGHT_OUTPUT_CONTROL, 6, OUTPUT_MUTE, 0, 1, 1, 0 }
896 },
897 [SOUND_MIXER_SPEAKER] = {
898 { CS_MONO_IO_CONTROL, 4, MONO_OUTPUT_MUTE, 0, 1, 1, 0 },
899 { CS_REG_NONE, 0, 0, 0, 0, 1, 0 }
900 },
901 [SOUND_MIXER_LINE] = {
902 { CS_LEFT_LINE_CONTROL, 5, LINE_INPUT_MUTE, 0, 1, 1, 1 },
903 { CS_RIGHT_LINE_CONTROL, 5, LINE_INPUT_MUTE, 0, 1, 1, 1 }
904 },
905 /*
906 * AUX1 : removed intentionally since it generates noises
907 * AUX2 : Ultra1/Ultra2 has no internal CD-ROM audio in
908 */
909 [SOUND_MIXER_CD] = {
910 { CS_LEFT_AUX2_CONTROL, 5, LINE_INPUT_MUTE, 0, 1, 1, 1 },
911 { CS_RIGHT_AUX2_CONTROL, 5, LINE_INPUT_MUTE, 0, 1, 1, 1 }
912 },
913 [SOUND_MIXER_MIC] = {
914 { CS_LEFT_INPUT_CONTROL, 4, 0, 0, 0, 1, 1 },
915 { CS_RIGHT_INPUT_CONTROL, 4, 0, 0, 0, 1, 1 }
916 },
917 [SOUND_MIXER_IGAIN] = {
918 { CS_LEFT_INPUT_CONTROL, 4, 0, 0, 1, 0 },
919 { CS_RIGHT_INPUT_CONTROL, 4, 0, 0, 1, 0 }
920 }
921 };
922
923 static int
cs4231_mixer_init(struct snd_mixer * m)924 cs4231_mixer_init(struct snd_mixer *m)
925 {
926 u_int32_t v;
927 int i;
928
929 v = 0;
930 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++)
931 if (cs4231_mix_table[i][0].avail != 0)
932 v |= (1 << i);
933 mix_setdevs(m, v);
934 v = 0;
935 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++)
936 if (cs4231_mix_table[i][0].recdev != 0)
937 v |= (1 << i);
938 mix_setrecdevs(m, v);
939 return (0);
940 }
941
942 static void
cs4231_mixer_set_value(struct cs4231_softc * sc,const struct mix_table * mt,u_int8_t v)943 cs4231_mixer_set_value(struct cs4231_softc *sc, const struct mix_table *mt,
944 u_int8_t v)
945 {
946 u_int8_t mask, reg;
947 u_int8_t old, shift, val;
948
949 if (mt->avail == 0 || mt->reg == CS_REG_NONE)
950 return;
951 reg = mt->reg;
952 if (mt->neg != 0)
953 val = 100 - v;
954 else
955 val = v;
956 mask = (1 << mt->bits) - 1;
957 val = ((val * mask) + 50) / 100;
958 shift = mt->shift;
959 val <<= shift;
960 if (v == 0)
961 val |= mt->mute;
962 old = cs4231_read(sc, reg);
963 old &= ~(mt->mute | (mask << shift));
964 val |= old;
965 if (reg == CS_LEFT_INPUT_CONTROL || reg == CS_RIGHT_INPUT_CONTROL) {
966 if ((val & (mask << shift)) != 0)
967 val |= ADC_INPUT_GAIN_ENABLE;
968 else
969 val &= ~ADC_INPUT_GAIN_ENABLE;
970 }
971 cs4231_write(sc, reg, val);
972 }
973
974 static int
cs4231_mixer_set(struct snd_mixer * m,u_int32_t dev,u_int32_t left,u_int32_t right)975 cs4231_mixer_set(struct snd_mixer *m, u_int32_t dev, u_int32_t left,
976 u_int32_t right)
977 {
978 struct cs4231_softc *sc;
979
980 sc = mix_getdevinfo(m);
981 CS4231_LOCK(sc);
982 cs4231_mixer_set_value(sc, &cs4231_mix_table[dev][0], left);
983 cs4231_mixer_set_value(sc, &cs4231_mix_table[dev][1], right);
984 CS4231_UNLOCK(sc);
985
986 return (left | (right << 8));
987 }
988
989 static u_int32_t
cs4231_mixer_setrecsrc(struct snd_mixer * m,u_int32_t src)990 cs4231_mixer_setrecsrc(struct snd_mixer *m, u_int32_t src)
991 {
992 struct cs4231_softc *sc;
993 u_int8_t v;
994
995 sc = mix_getdevinfo(m);
996 switch (src) {
997 case SOUND_MASK_LINE:
998 v = CS_IN_LINE;
999 break;
1000
1001 case SOUND_MASK_CD:
1002 v = CS_IN_DAC;
1003 break;
1004
1005 case SOUND_MASK_MIC:
1006 default:
1007 v = CS_IN_MIC;
1008 src = SOUND_MASK_MIC;
1009 break;
1010 }
1011 CS4231_LOCK(sc);
1012 cs4231_write(sc, CS_LEFT_INPUT_CONTROL,
1013 (cs4231_read(sc, CS_LEFT_INPUT_CONTROL) & CS_IN_MASK) | v);
1014 cs4231_write(sc, CS_RIGHT_INPUT_CONTROL,
1015 (cs4231_read(sc, CS_RIGHT_INPUT_CONTROL) & CS_IN_MASK) | v);
1016 CS4231_UNLOCK(sc);
1017
1018 return (src);
1019 }
1020
1021 static void *
cs4231_chan_init(kobj_t obj,void * dev,struct snd_dbuf * b,struct pcm_channel * c,int dir)1022 cs4231_chan_init(kobj_t obj, void *dev, struct snd_dbuf *b,
1023 struct pcm_channel *c, int dir)
1024 {
1025 struct cs4231_softc *sc;
1026 struct cs4231_channel *ch;
1027 bus_dma_tag_t dmat;
1028
1029 sc = dev;
1030 ch = (dir == PCMDIR_PLAY) ? &sc->sc_pch : &sc->sc_rch;
1031 ch->parent = sc;
1032 ch->channel = c;
1033 ch->dir = dir;
1034 ch->buffer = b;
1035 if ((sc->sc_flags & CS4231_SBUS) != 0)
1036 dmat = sc->sc_dmat[0];
1037 else {
1038 if (dir == PCMDIR_PLAY)
1039 dmat = sc->sc_dmat[1];
1040 else
1041 dmat = sc->sc_dmat[0];
1042 }
1043 if (sndbuf_alloc(ch->buffer, dmat, 0, sc->sc_bufsz) != 0)
1044 return (NULL);
1045 DPRINTF(("%s channel addr: 0x%lx\n", dir == PCMDIR_PLAY ? "playback" :
1046 "capture", sndbuf_getbufaddr(ch->buffer)));
1047
1048 return (ch);
1049 }
1050
1051 static int
cs4231_chan_setformat(kobj_t obj,void * data,u_int32_t format)1052 cs4231_chan_setformat(kobj_t obj, void *data, u_int32_t format)
1053 {
1054 struct cs4231_softc *sc;
1055 struct cs4231_channel *ch;
1056 u_int32_t encoding;
1057 u_int8_t fs, v;
1058
1059 ch = data;
1060 sc = ch->parent;
1061
1062 CS4231_LOCK(sc);
1063 if (ch->format == format) {
1064 CS4231_UNLOCK(sc);
1065 return (0);
1066 }
1067
1068 encoding = AFMT_ENCODING(format);
1069 fs = 0;
1070 switch (encoding) {
1071 case AFMT_U8:
1072 fs = CS_AFMT_U8;
1073 break;
1074 case AFMT_MU_LAW:
1075 fs = CS_AFMT_MU_LAW;
1076 break;
1077 case AFMT_S16_LE:
1078 fs = CS_AFMT_S16_LE;
1079 break;
1080 case AFMT_A_LAW:
1081 fs = CS_AFMT_A_LAW;
1082 break;
1083 case AFMT_IMA_ADPCM:
1084 fs = CS_AFMT_IMA_ADPCM;
1085 break;
1086 case AFMT_S16_BE:
1087 fs = CS_AFMT_S16_BE;
1088 break;
1089 default:
1090 fs = CS_AFMT_U8;
1091 format = AFMT_U8;
1092 break;
1093 }
1094
1095 if (AFMT_CHANNEL(format) > 1)
1096 fs |= CS_AFMT_STEREO;
1097
1098 DPRINTF(("FORMAT: %s : 0x%x\n", ch->dir == PCMDIR_PLAY ? "playback" :
1099 "capture", format));
1100 v = cs4231_read(sc, CS_CLOCK_DATA_FORMAT);
1101 v &= CS_CLOCK_DATA_FORMAT_MASK;
1102 fs |= v;
1103 cs4231_chan_fs(sc, ch->dir, fs);
1104 ch->format = format;
1105 CS4231_UNLOCK(sc);
1106
1107 return (0);
1108 }
1109
1110 static u_int32_t
cs4231_chan_setspeed(kobj_t obj,void * data,u_int32_t speed)1111 cs4231_chan_setspeed(kobj_t obj, void *data, u_int32_t speed)
1112 {
1113 typedef struct {
1114 u_int32_t speed;
1115 u_int8_t bits;
1116 } speed_struct;
1117
1118 const static speed_struct speed_table[] = {
1119 {5510, (0 << 1) | CLOCK_XTAL2},
1120 {5510, (0 << 1) | CLOCK_XTAL2},
1121 {6620, (7 << 1) | CLOCK_XTAL2},
1122 {8000, (0 << 1) | CLOCK_XTAL1},
1123 {9600, (7 << 1) | CLOCK_XTAL1},
1124 {11025, (1 << 1) | CLOCK_XTAL2},
1125 {16000, (1 << 1) | CLOCK_XTAL1},
1126 {18900, (2 << 1) | CLOCK_XTAL2},
1127 {22050, (3 << 1) | CLOCK_XTAL2},
1128 {27420, (2 << 1) | CLOCK_XTAL1},
1129 {32000, (3 << 1) | CLOCK_XTAL1},
1130 {33075, (6 << 1) | CLOCK_XTAL2},
1131 {33075, (4 << 1) | CLOCK_XTAL2},
1132 {44100, (5 << 1) | CLOCK_XTAL2},
1133 {48000, (6 << 1) | CLOCK_XTAL1},
1134 };
1135
1136 struct cs4231_softc *sc;
1137 struct cs4231_channel *ch;
1138 int i, n, sel;
1139 u_int8_t fs;
1140
1141 ch = data;
1142 sc = ch->parent;
1143 CS4231_LOCK(sc);
1144 if (ch->speed == speed) {
1145 CS4231_UNLOCK(sc);
1146 return (speed);
1147 }
1148 n = sizeof(speed_table) / sizeof(speed_struct);
1149
1150 for (i = 1, sel =0; i < n - 1; i++)
1151 if (abs(speed - speed_table[i].speed) <
1152 abs(speed - speed_table[sel].speed))
1153 sel = i;
1154 DPRINTF(("SPEED: %s : %dHz -> %dHz\n", ch->dir == PCMDIR_PLAY ?
1155 "playback" : "capture", speed, speed_table[sel].speed));
1156 speed = speed_table[sel].speed;
1157
1158 fs = cs4231_read(sc, CS_CLOCK_DATA_FORMAT);
1159 fs &= ~CS_CLOCK_DATA_FORMAT_MASK;
1160 fs |= speed_table[sel].bits;
1161 cs4231_chan_fs(sc, ch->dir, fs);
1162 ch->speed = speed;
1163 CS4231_UNLOCK(sc);
1164
1165 return (speed);
1166 }
1167
1168 static void
cs4231_chan_fs(struct cs4231_softc * sc,int dir,u_int8_t fs)1169 cs4231_chan_fs(struct cs4231_softc *sc, int dir, u_int8_t fs)
1170 {
1171 int i, doreset;
1172 #ifdef CS4231_AUTO_CALIBRATION
1173 u_int8_t v;
1174 #endif
1175
1176 CS4231_LOCK_ASSERT(sc);
1177
1178 /* set autocalibration */
1179 doreset = 0;
1180 #ifdef CS4231_AUTO_CALIBRATION
1181 v = cs4231_read(sc, CS_INTERFACE_CONFIG) | AUTO_CAL_ENABLE;
1182 CS_WRITE(sc, CS4231_IADDR, MODE_CHANGE_ENABLE);
1183 CS_WRITE(sc, CS4231_IADDR, MODE_CHANGE_ENABLE | CS_INTERFACE_CONFIG);
1184 CS_WRITE(sc, CS4231_IDATA, v);
1185 #endif
1186
1187 /*
1188 * We always need to write CS_CLOCK_DATA_FORMAT register since
1189 * the clock frequency is shared with playback/capture.
1190 */
1191 CS_WRITE(sc, CS4231_IADDR, MODE_CHANGE_ENABLE | CS_CLOCK_DATA_FORMAT);
1192 CS_WRITE(sc, CS4231_IDATA, fs);
1193 CS_READ(sc, CS4231_IDATA);
1194 CS_READ(sc, CS4231_IDATA);
1195 for (i = CS_TIMEOUT;
1196 i && CS_READ(sc, CS4231_IADDR) == CS_IN_INIT; i--)
1197 DELAY(10);
1198 if (i == 0) {
1199 device_printf(sc->sc_dev, "timeout setting playback speed\n");
1200 doreset++;
1201 }
1202
1203 /*
1204 * capture channel
1205 * cs4231 doesn't allow separate fs setup for playback/capture.
1206 * I believe this will break full-duplex operation.
1207 */
1208 if (dir == PCMDIR_REC) {
1209 CS_WRITE(sc, CS4231_IADDR, MODE_CHANGE_ENABLE | CS_REC_FORMAT);
1210 CS_WRITE(sc, CS4231_IDATA, fs);
1211 CS_READ(sc, CS4231_IDATA);
1212 CS_READ(sc, CS4231_IDATA);
1213 for (i = CS_TIMEOUT;
1214 i && CS_READ(sc, CS4231_IADDR) == CS_IN_INIT; i--)
1215 DELAY(10);
1216 if (i == 0) {
1217 device_printf(sc->sc_dev,
1218 "timeout setting capture format\n");
1219 doreset++;
1220 }
1221 }
1222
1223 CS_WRITE(sc, CS4231_IADDR, 0);
1224 for (i = CS_TIMEOUT;
1225 i && CS_READ(sc, CS4231_IADDR) == CS_IN_INIT; i--)
1226 DELAY(10);
1227 if (i == 0) {
1228 device_printf(sc->sc_dev, "timeout waiting for !MCE\n");
1229 doreset++;
1230 }
1231
1232 #ifdef CS4231_AUTO_CALIBRATION
1233 CS_WRITE(sc, CS4231_IADDR, CS_TEST_AND_INIT);
1234 for (i = CS_TIMEOUT;
1235 i && CS_READ(sc, CS4231_IDATA) & AUTO_CAL_IN_PROG; i--)
1236 DELAY(10);
1237 if (i == 0) {
1238 device_printf(sc->sc_dev,
1239 "timeout waiting for autocalibration\n");
1240 doreset++;
1241 }
1242 #endif
1243 if (doreset) {
1244 /*
1245 * Maybe the last resort to avoid a dreadful message like
1246 * "pcm0:play:0: play interrupt timeout, channel dead" would
1247 * be hardware reset.
1248 */
1249 device_printf(sc->sc_dev, "trying to hardware reset\n");
1250 cs4231_disable(sc);
1251 cs4231_enable(sc, CODEC_COLD_RESET);
1252 CS4231_UNLOCK(sc); /* XXX */
1253 if (mixer_reinit(sc->sc_dev) != 0)
1254 device_printf(sc->sc_dev,
1255 "unable to reinitialize the mixer\n");
1256 CS4231_LOCK(sc);
1257 }
1258 }
1259
1260 static u_int32_t
cs4231_chan_setblocksize(kobj_t obj,void * data,u_int32_t blocksize)1261 cs4231_chan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
1262 {
1263 struct cs4231_softc *sc;
1264 struct cs4231_channel *ch;
1265 int nblks, error;
1266
1267 ch = data;
1268 sc = ch->parent;
1269
1270 if (blocksize > CS4231_MAX_BLK_SZ)
1271 blocksize = CS4231_MAX_BLK_SZ;
1272 nblks = sc->sc_bufsz / blocksize;
1273 error = sndbuf_resize(ch->buffer, nblks, blocksize);
1274 if (error != 0)
1275 device_printf(sc->sc_dev,
1276 "unable to block size, blksz = %d, error = %d\n",
1277 blocksize, error);
1278
1279 return (blocksize);
1280 }
1281
1282 static int
cs4231_chan_trigger(kobj_t obj,void * data,int go)1283 cs4231_chan_trigger(kobj_t obj, void *data, int go)
1284 {
1285 struct cs4231_channel *ch;
1286
1287 ch = data;
1288 switch (go) {
1289 case PCMTRIG_EMLDMAWR:
1290 case PCMTRIG_EMLDMARD:
1291 break;
1292 case PCMTRIG_START:
1293 cs4231_trigger(ch);
1294 break;
1295 case PCMTRIG_ABORT:
1296 case PCMTRIG_STOP:
1297 cs4231_halt(ch);
1298 break;
1299 default:
1300 break;
1301 }
1302
1303 return (0);
1304 }
1305
1306 static u_int32_t
cs4231_chan_getptr(kobj_t obj,void * data)1307 cs4231_chan_getptr(kobj_t obj, void *data)
1308 {
1309 struct cs4231_softc *sc;
1310 struct cs4231_channel *ch;
1311 u_int32_t cur, ptr, sz;
1312
1313 ch = data;
1314 sc = ch->parent;
1315
1316 CS4231_LOCK(sc);
1317 if ((sc->sc_flags & CS4231_SBUS) != 0)
1318 cur = (ch->dir == PCMDIR_PLAY) ? APC_READ(sc, APC_PVA) :
1319 APC_READ(sc, APC_CVA);
1320 else
1321 cur = (ch->dir == PCMDIR_PLAY) ? EBDMA_P_READ(sc, EBDMA_DADDR) :
1322 EBDMA_C_READ(sc, EBDMA_DADDR);
1323 sz = sndbuf_getsize(ch->buffer);
1324 ptr = cur - sndbuf_getbufaddr(ch->buffer) + sz;
1325 CS4231_UNLOCK(sc);
1326
1327 ptr %= sz;
1328 return (ptr);
1329 }
1330
1331 static struct pcmchan_caps *
cs4231_chan_getcaps(kobj_t obj,void * data)1332 cs4231_chan_getcaps(kobj_t obj, void *data)
1333 {
1334
1335 return (&cs4231_caps);
1336 }
1337
1338 static void
cs4231_trigger(struct cs4231_channel * ch)1339 cs4231_trigger(struct cs4231_channel *ch)
1340 {
1341 struct cs4231_softc *sc;
1342
1343 sc = ch->parent;
1344 if ((sc->sc_flags & CS4231_SBUS) != 0)
1345 cs4231_apcdma_trigger(sc, ch);
1346 else
1347 cs4231_ebdma_trigger(sc, ch);
1348 }
1349
1350 static void
cs4231_apcdma_trigger(struct cs4231_softc * sc,struct cs4231_channel * ch)1351 cs4231_apcdma_trigger(struct cs4231_softc *sc, struct cs4231_channel *ch)
1352 {
1353 u_int32_t csr, togo;
1354 u_int32_t nextaddr;
1355
1356 CS4231_LOCK(sc);
1357 if (ch->locked) {
1358 device_printf(sc->sc_dev, "%s channel already triggered\n",
1359 ch->dir == PCMDIR_PLAY ? "playback" : "capture");
1360 CS4231_UNLOCK(sc);
1361 return;
1362 }
1363
1364 nextaddr = sndbuf_getbufaddr(ch->buffer);
1365 togo = sndbuf_getsize(ch->buffer) / 2;
1366 if (togo > CS4231_MAX_APC_DMA_SZ)
1367 togo = CS4231_MAX_APC_DMA_SZ;
1368 ch->togo = togo;
1369 if (ch->dir == PCMDIR_PLAY) {
1370 DPRINTF(("TRG: PNVA = 0x%x, togo = 0x%x\n", nextaddr, togo));
1371
1372 cs4231_read(sc, CS_TEST_AND_INIT); /* clear pending error */
1373 csr = APC_READ(sc, APC_CSR);
1374 APC_WRITE(sc, APC_PNVA, nextaddr);
1375 APC_WRITE(sc, APC_PNC, togo);
1376
1377 if ((csr & APC_CSR_PDMA_GO) == 0 ||
1378 (csr & APC_CSR_PPAUSE) != 0) {
1379 APC_WRITE(sc, APC_CSR, APC_READ(sc, APC_CSR) &
1380 ~(APC_CSR_PIE | APC_CSR_PPAUSE));
1381 APC_WRITE(sc, APC_CSR, APC_READ(sc, APC_CSR) |
1382 APC_CSR_GIE | APC_CSR_PIE | APC_CSR_EIE |
1383 APC_CSR_EI | APC_CSR_PMIE | APC_CSR_PDMA_GO);
1384 cs4231_write(sc, CS_INTERFACE_CONFIG,
1385 cs4231_read(sc, CS_INTERFACE_CONFIG) |
1386 PLAYBACK_ENABLE);
1387 }
1388 /* load next address */
1389 if (APC_READ(sc, APC_CSR) & APC_CSR_PD) {
1390 nextaddr += togo;
1391 APC_WRITE(sc, APC_PNVA, nextaddr);
1392 APC_WRITE(sc, APC_PNC, togo);
1393 }
1394 } else {
1395 DPRINTF(("TRG: CNVA = 0x%x, togo = 0x%x\n", nextaddr, togo));
1396
1397 cs4231_read(sc, CS_TEST_AND_INIT); /* clear pending error */
1398 APC_WRITE(sc, APC_CNVA, nextaddr);
1399 APC_WRITE(sc, APC_CNC, togo);
1400 csr = APC_READ(sc, APC_CSR);
1401 if ((csr & APC_CSR_CDMA_GO) == 0 ||
1402 (csr & APC_CSR_CPAUSE) != 0) {
1403 csr &= APC_CSR_CPAUSE;
1404 csr |= APC_CSR_GIE | APC_CSR_CMIE | APC_CSR_CIE |
1405 APC_CSR_EI | APC_CSR_CDMA_GO;
1406 APC_WRITE(sc, APC_CSR, csr);
1407 cs4231_write(sc, CS_INTERFACE_CONFIG,
1408 cs4231_read(sc, CS_INTERFACE_CONFIG) |
1409 CAPTURE_ENABLE);
1410 }
1411 /* load next address */
1412 if (APC_READ(sc, APC_CSR) & APC_CSR_CD) {
1413 nextaddr += togo;
1414 APC_WRITE(sc, APC_CNVA, nextaddr);
1415 APC_WRITE(sc, APC_CNC, togo);
1416 }
1417 }
1418 ch->nextaddr = nextaddr;
1419 ch->locked = 1;
1420 CS4231_UNLOCK(sc);
1421 }
1422
1423 static void
cs4231_ebdma_trigger(struct cs4231_softc * sc,struct cs4231_channel * ch)1424 cs4231_ebdma_trigger(struct cs4231_softc *sc, struct cs4231_channel *ch)
1425 {
1426 u_int32_t csr, togo;
1427 u_int32_t nextaddr;
1428
1429 CS4231_LOCK(sc);
1430 if (ch->locked) {
1431 device_printf(sc->sc_dev, "%s channel already triggered\n",
1432 ch->dir == PCMDIR_PLAY ? "playback" : "capture");
1433 CS4231_UNLOCK(sc);
1434 return;
1435 }
1436
1437 nextaddr = sndbuf_getbufaddr(ch->buffer);
1438 togo = sndbuf_getsize(ch->buffer) / 2;
1439 if (togo % 64 == 0)
1440 sc->sc_burst = EBDCSR_BURST_16;
1441 else if (togo % 32 == 0)
1442 sc->sc_burst = EBDCSR_BURST_8;
1443 else if (togo % 16 == 0)
1444 sc->sc_burst = EBDCSR_BURST_4;
1445 else
1446 sc->sc_burst = EBDCSR_BURST_1;
1447 ch->togo = togo;
1448 DPRINTF(("TRG: DNAR = 0x%x, togo = 0x%x\n", nextaddr, togo));
1449 if (ch->dir == PCMDIR_PLAY) {
1450 cs4231_read(sc, CS_TEST_AND_INIT); /* clear pending error */
1451 csr = EBDMA_P_READ(sc, EBDMA_DCSR);
1452
1453 if (csr & EBDCSR_DMAEN) {
1454 EBDMA_P_WRITE(sc, EBDMA_DCNT, togo);
1455 EBDMA_P_WRITE(sc, EBDMA_DADDR, nextaddr);
1456 } else {
1457 EBDMA_P_WRITE(sc, EBDMA_DCSR, EBDCSR_RESET);
1458 EBDMA_P_WRITE(sc, EBDMA_DCSR, sc->sc_burst);
1459 EBDMA_P_WRITE(sc, EBDMA_DCNT, togo);
1460 EBDMA_P_WRITE(sc, EBDMA_DADDR, nextaddr);
1461
1462 EBDMA_P_WRITE(sc, EBDMA_DCSR, sc->sc_burst |
1463 EBDCSR_DMAEN | EBDCSR_INTEN | EBDCSR_CNTEN |
1464 EBDCSR_NEXTEN);
1465 cs4231_write(sc, CS_INTERFACE_CONFIG,
1466 cs4231_read(sc, CS_INTERFACE_CONFIG) |
1467 PLAYBACK_ENABLE);
1468 }
1469 /* load next address */
1470 if (EBDMA_P_READ(sc, EBDMA_DCSR) & EBDCSR_A_LOADED) {
1471 nextaddr += togo;
1472 EBDMA_P_WRITE(sc, EBDMA_DCNT, togo);
1473 EBDMA_P_WRITE(sc, EBDMA_DADDR, nextaddr);
1474 }
1475 } else {
1476 cs4231_read(sc, CS_TEST_AND_INIT); /* clear pending error */
1477 csr = EBDMA_C_READ(sc, EBDMA_DCSR);
1478
1479 if (csr & EBDCSR_DMAEN) {
1480 EBDMA_C_WRITE(sc, EBDMA_DCNT, togo);
1481 EBDMA_C_WRITE(sc, EBDMA_DADDR, nextaddr);
1482 } else {
1483 EBDMA_C_WRITE(sc, EBDMA_DCSR, EBDCSR_RESET);
1484 EBDMA_C_WRITE(sc, EBDMA_DCSR, sc->sc_burst);
1485 EBDMA_C_WRITE(sc, EBDMA_DCNT, togo);
1486 EBDMA_C_WRITE(sc, EBDMA_DADDR, nextaddr);
1487
1488 EBDMA_C_WRITE(sc, EBDMA_DCSR, sc->sc_burst |
1489 EBDCSR_WRITE | EBDCSR_DMAEN | EBDCSR_INTEN |
1490 EBDCSR_CNTEN | EBDCSR_NEXTEN);
1491 cs4231_write(sc, CS_INTERFACE_CONFIG,
1492 cs4231_read(sc, CS_INTERFACE_CONFIG) |
1493 CAPTURE_ENABLE);
1494 }
1495 /* load next address */
1496 if (EBDMA_C_READ(sc, EBDMA_DCSR) & EBDCSR_A_LOADED) {
1497 nextaddr += togo;
1498 EBDMA_C_WRITE(sc, EBDMA_DCNT, togo);
1499 EBDMA_C_WRITE(sc, EBDMA_DADDR, nextaddr);
1500 }
1501 }
1502 ch->nextaddr = nextaddr;
1503 ch->locked = 1;
1504 CS4231_UNLOCK(sc);
1505 }
1506
1507 static void
cs4231_halt(struct cs4231_channel * ch)1508 cs4231_halt(struct cs4231_channel *ch)
1509 {
1510 struct cs4231_softc *sc;
1511 u_int8_t status;
1512 int i;
1513
1514 sc = ch->parent;
1515 CS4231_LOCK(sc);
1516 if (ch->locked == 0) {
1517 CS4231_UNLOCK(sc);
1518 return;
1519 }
1520
1521 if (ch->dir == PCMDIR_PLAY ) {
1522 if ((sc->sc_flags & CS4231_SBUS) != 0) {
1523 /* XXX Kills some capture bits */
1524 APC_WRITE(sc, APC_CSR, APC_READ(sc, APC_CSR) &
1525 ~(APC_CSR_EI | APC_CSR_GIE | APC_CSR_PIE |
1526 APC_CSR_EIE | APC_CSR_PDMA_GO | APC_CSR_PMIE));
1527 } else {
1528 EBDMA_P_WRITE(sc, EBDMA_DCSR,
1529 EBDMA_P_READ(sc, EBDMA_DCSR) & ~EBDCSR_DMAEN);
1530 }
1531 /* Waiting for playback FIFO to empty */
1532 status = cs4231_read(sc, CS_TEST_AND_INIT);
1533 for (i = CS_TIMEOUT;
1534 i && (status & PLAYBACK_UNDERRUN) == 0; i--) {
1535 DELAY(5);
1536 status = cs4231_read(sc, CS_TEST_AND_INIT);
1537 }
1538 if (i == 0)
1539 device_printf(sc->sc_dev, "timeout waiting for "
1540 "playback FIFO drain\n");
1541 cs4231_write(sc, CS_INTERFACE_CONFIG,
1542 cs4231_read(sc, CS_INTERFACE_CONFIG) & (~PLAYBACK_ENABLE));
1543 } else {
1544 if ((sc->sc_flags & CS4231_SBUS) != 0) {
1545 /* XXX Kills some playback bits */
1546 APC_WRITE(sc, APC_CSR, APC_CSR_CAPTURE_PAUSE);
1547 } else {
1548 EBDMA_C_WRITE(sc, EBDMA_DCSR,
1549 EBDMA_C_READ(sc, EBDMA_DCSR) & ~EBDCSR_DMAEN);
1550 }
1551 /* Waiting for capture FIFO to empty */
1552 status = cs4231_read(sc, CS_TEST_AND_INIT);
1553 for (i = CS_TIMEOUT;
1554 i && (status & CAPTURE_OVERRUN) == 0; i--) {
1555 DELAY(5);
1556 status = cs4231_read(sc, CS_TEST_AND_INIT);
1557 }
1558 if (i == 0)
1559 device_printf(sc->sc_dev, "timeout waiting for "
1560 "capture FIFO drain\n");
1561 cs4231_write(sc, CS_INTERFACE_CONFIG,
1562 cs4231_read(sc, CS_INTERFACE_CONFIG) & (~CAPTURE_ENABLE));
1563 }
1564 ch->locked = 0;
1565 CS4231_UNLOCK(sc);
1566 }
1567