Searched refs:cacheline (Results 1 – 7 of 7) sorted by relevance
92 options USB_HOST_ALIGN=32 # Align DMA to cacheline
96 options USB_HOST_ALIGN=32 # Align DMA to cacheline
2036 uint32_t cacheline; in ti_chipinit() local2104 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; in ti_chipinit()2113 switch (cacheline) { in ti_chipinit()2126 cacheline); in ti_chipinit()
758 * We fetch a "cacheline aligned" and sized amount of data762 * cacheline size is unknown.799 * If the ending address is on a cacheline boundary,
1304 * Partial transfer past cacheline end to be
1523 * We fetch a "cacheline aligned" and sized amount of data1527 * cacheline size is unknown.
1102 "arenas.cacheline", "arenas.subpage", "arenas.[tqcs]space_{min,max}", and