Searched refs:ZIP1 (Results 1 – 6 of 6) sorted by relevance
| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 102 ZIP1, enumerator
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| H A D | AArch64SchedKryoDetails.td | 2330 (instregex "((TRN1|TRN2|ZIP1|UZP1|UZP2)v2i64|ZIP2(v2i64|v4i32|v8i16|v16i8))")>; 2366 (instregex "(UZP1|UZP2|ZIP1|ZIP2)(v2i32|v4i16|v8i8)")>; 2378 (instregex "ZIP1(v4i32|v8i16|v16i8)")>;
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| H A D | AArch64SchedFalkorDetails.td | 921 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(TRN1|TRN2|ZIP1|UZP1|UZP2|ZIP2|XTN)(v2i32|v2i64|…
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| H A D | AArch64ISelLowering.cpp | 1131 case AArch64ISD::ZIP1: return "AArch64ISD::ZIP1"; in getTargetNodeName() 6494 return DAG.getNode(AArch64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS, in GeneratePerfectShuffle() 6656 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2; in LowerVECTOR_SHUFFLE() 6669 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2; in LowerVECTOR_SHUFFLE()
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| H A D | AArch64SchedThunderX2T99.td | 1538 (instregex "^UZP1", "^UZP2", "^ZIP1", "^ZIP2")>;
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| H A D | AArch64InstrInfo.td | 303 def AArch64zip1 : SDNode<"AArch64ISD::ZIP1", SDT_AArch64Zip>; 4312 defm ZIP1 : SIMDZipVector<0b011, "zip1", AArch64zip1>;
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