| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 473 bool shouldTransformSignedTruncationCheck(EVT XVT, in shouldTransformSignedTruncationCheck() argument
476 if (XVT.isVector()) in shouldTransformSignedTruncationCheck()
487 return VTIsOk(XVT) && VTIsOk(KeptBitsVT); in shouldTransformSignedTruncationCheck()
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| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 2960 MVT XVT = NVT; in matchBitExtract() local
2965 XVT = X.getSimpleValueType(); in matchBitExtract()
2966 assert(XVT == MVT::i64 && "Expected truncation from i64"); in matchBitExtract()
2970 if (NBits.getValueType() != XVT) { in matchBitExtract()
2981 CurDAG->getTargetInsertSubreg(X86::sub_8bit, DL, XVT, ImplDef, NBits); in matchBitExtract()
2987 SDValue Extract = CurDAG->getNode(X86ISD::BZHI, DL, XVT, X, NBits); in matchBitExtract()
3002 SDValue Control = CurDAG->getNode(ISD::SHL, DL, XVT, NBits, C8); in matchBitExtract()
3015 ShiftAmt = CurDAG->getNode(ISD::ZERO_EXTEND, DL, XVT, ShiftAmt); in matchBitExtract()
3019 Control = CurDAG->getNode(ISD::OR, DL, XVT, Control, ShiftAmt); in matchBitExtract()
3024 SDValue Extract = CurDAG->getNode(X86ISD::BEXTR, DL, XVT, X, Control); in matchBitExtract()
[all …]
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| H A D | X86ISelLowering.h | 816 shouldTransformSignedTruncationCheck(EVT XVT, in shouldTransformSignedTruncationCheck() argument
819 if (XVT.isVector()) in shouldTransformSignedTruncationCheck()
830 return VTIsOk(XVT) && VTIsOk(KeptBitsVT); in shouldTransformSignedTruncationCheck()
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 2134 EVT XVT = X.getValueType(); in optimizeSetCCOfSignedTruncationCheck() local
2182 assert(KeptBits > 0 && KeptBits < XVT.getSizeInBits() && "unreachable"); in optimizeSetCCOfSignedTruncationCheck()
2187 XVT, KeptBits)) in optimizeSetCCOfSignedTruncationCheck()
2190 const unsigned MaskedBits = XVT.getSizeInBits() - KeptBits; in optimizeSetCCOfSignedTruncationCheck()
2191 assert(MaskedBits > 0 && MaskedBits < XVT.getSizeInBits() && "unreachable"); in optimizeSetCCOfSignedTruncationCheck()
2195 SDValue ShiftAmt = DAG.getConstant(MaskedBits, DL, XVT); in optimizeSetCCOfSignedTruncationCheck()
2196 SDValue T0 = DAG.getNode(ISD::SHL, DL, XVT, X, ShiftAmt); in optimizeSetCCOfSignedTruncationCheck()
2197 SDValue T1 = DAG.getNode(ISD::SRA, DL, XVT, T0, ShiftAmt); in optimizeSetCCOfSignedTruncationCheck()
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| H A D | DAGCombiner.cpp | 3840 EVT XVT = X.getValueType(); in hoistLogicOpWithSameOpcodeHands() local
3849 if (XVT != Y.getValueType()) in hoistLogicOpWithSameOpcodeHands()
3854 !TLI.isOperationLegalOrCustom(LogicOpcode, XVT)) in hoistLogicOpWithSameOpcodeHands()
3859 !TLI.isTypeDesirableForOp(LogicOpcode, XVT)) in hoistLogicOpWithSameOpcodeHands()
3862 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y); in hoistLogicOpWithSameOpcodeHands()
3873 if (XVT != Y.getValueType()) in hoistLogicOpWithSameOpcodeHands()
3880 if (TLI.isZExtFree(VT, XVT) && TLI.isTruncateFree(XVT, VT)) in hoistLogicOpWithSameOpcodeHands()
3882 if (!TLI.isTypeLegal(XVT)) in hoistLogicOpWithSameOpcodeHands()
3884 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y); in hoistLogicOpWithSameOpcodeHands()
3919 if (XVT.isInteger() && XVT == Y.getValueType()) { in hoistLogicOpWithSameOpcodeHands()
[all …]
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| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 538 virtual bool shouldTransformSignedTruncationCheck(EVT XVT, in shouldTransformSignedTruncationCheck() argument
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 2987 EVT XVT = X.getValueType(); in performShlCombine() local
2988 SDValue Shl = DAG.getNode(ISD::SHL, SL, XVT, X, SDValue(RHS, 0)); in performShlCombine()
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