| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMScheduleA57.td | 80 list <SchedWriteRes> Writes = writes;
575 SchedVar<A57LMAddrPred1, A57LDMOpsList_Upd.Writes[0-2]>,
849 SchedVar<A57LMAddrPred1, A57VLDMOpsListCond.Writes[0-1]>,
850 SchedVar<A57LMAddrPred2, A57VLDMOpsListCond.Writes[0-3]>,
851 SchedVar<A57LMAddrPred3, A57VLDMOpsListCond.Writes[0-5]>,
852 SchedVar<A57LMAddrPred4, A57VLDMOpsListCond.Writes[0-7]>,
853 SchedVar<A57LMAddrPred5, A57VLDMOpsListCond.Writes[0-9]>,
854 SchedVar<A57LMAddrPred6, A57VLDMOpsListCond.Writes[0-11]>,
855 SchedVar<A57LMAddrPred7, A57VLDMOpsListCond.Writes[0-13]>,
856 SchedVar<A57LMAddrPred8, A57VLDMOpsListCond.Writes[0-15]>,
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| H A D | ARMParallelDSP.cpp | 554 Instructions &Writes) { in AliasCandidates() argument
559 Writes.push_back(&I); in AliasCandidates()
567 Instructions &Writes, OpChainList &MACCandidates) { in AreAliased() argument
580 for (auto *I : Writes) { in AreAliased()
677 Instructions Reads, Writes; in MatchSMLAD() local
678 AliasCandidates(Header, Reads, Writes); in MatchSMLAD()
681 if (AreAliased(AA, Reads, Writes, R.MACCandidates)) in MatchSMLAD()
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| H A D | ARMScheduleA9.td | 1883 list <WriteSequence> Writes = writes;
2111 SchedVar<A9LMAdr1Pred, A9WriteLMOpsList.Writes[0-1]>,
2112 SchedVar<A9LMAdr2Pred, A9WriteLMOpsList.Writes[0-3]>,
2113 SchedVar<A9LMAdr3Pred, A9WriteLMOpsList.Writes[0-5]>,
2114 SchedVar<A9LMAdr4Pred, A9WriteLMOpsList.Writes[0-7]>,
2115 SchedVar<A9LMAdr5Pred, A9WriteLMOpsList.Writes[0-9]>,
2116 SchedVar<A9LMAdr6Pred, A9WriteLMOpsList.Writes[0-11]>,
2117 SchedVar<A9LMAdr7Pred, A9WriteLMOpsList.Writes[0-13]>,
2118 SchedVar<A9LMAdr8Pred, A9WriteLMOpsList.Writes[0-15]>,
2216 SchedVar<A9LMAdr1Pred, A9WriteLMfpPostRAOpsList.Writes[0-0, 8-8]>,
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| /freebsd-12.1/contrib/llvm/lib/MCA/HardwareUnits/ |
| H A D | RegisterFile.cpp | 363 SmallVectorImpl<WriteRef> &Writes) const { in collectWrites()
376 Writes.push_back(WR); in collectWrites()
382 Writes.push_back(WR); in collectWrites()
386 if (Writes.size() > 1) { in collectWrites()
387 sort(Writes, [](const WriteRef &Lhs, const WriteRef &Rhs) { in collectWrites()
390 auto It = std::unique(Writes.begin(), Writes.end()); in collectWrites()
391 Writes.resize(std::distance(Writes.begin(), It)); in collectWrites()
395 for (const WriteRef &WR : Writes) { in collectWrites()
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| /freebsd-12.1/contrib/llvm/utils/TableGen/ |
| H A D | CodeGenSchedule.cpp | 880 IdxVec Writes, Reads; in collectSchedClasses() local
926 if (!SC.Writes.empty()) { in collectSchedClasses()
930 for (IdxIter WI = SC.Writes.begin(), WE = SC.Writes.end(); WI != WE; in collectSchedClasses()
945 IdxVec Writes; in collectSchedClasses() local
948 Writes, Reads); in collectSchedClasses()
1037 SC.Writes = OperWrites; in addSchedClass()
1112 SC.Writes = SchedClasses[OldSCIdx].Writes; in createInstRWClass()
1257 IdxVec Writes, Reads; in inferFromItinClass() local
1279 IdxVec Writes, Reads; in inferFromInstRWs() local
1841 IdxVec Writes, Reads; in collectProcResources() local
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| H A D | CodeGenSchedule.h | 131 IdxVec Writes; member
149 return ItinClassDef == IC && makeArrayRef(Writes) == W && in isKeyEqual()
558 void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const;
634 void collectRWResources(ArrayRef<unsigned> Writes, ArrayRef<unsigned> Reads,
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| H A D | SubtargetEmitter.cpp | 1003 IdxVec Writes = SC.Writes; in GenSchedClassTables() local
1017 Writes.clear(); in GenSchedClassTables()
1020 Writes, Reads); in GenSchedClassTables()
1023 if (Writes.empty()) { in GenSchedClassTables()
1029 Writes, Reads); in GenSchedClassTables()
1033 if (Writes.empty()) { in GenSchedClassTables()
1044 for (unsigned W : Writes) { in GenSchedClassTables()
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| /freebsd-12.1/contrib/llvm/lib/MC/ |
| H A D | MCInstrAnalysis.cpp | 22 APInt &Writes) const { in clearsSuperRegisters()
23 Writes.clearAllBits(); in clearsSuperRegisters()
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| /freebsd-12.1/contrib/llvm/lib/MCA/ |
| H A D | InstrBuilder.cpp | 290 ID.Writes.resize(TotalDefs + NumVariadicOps); in populateWrites()
301 WriteDescriptor &Write = ID.Writes[CurrentDef]; in populateWrites()
328 WriteDescriptor &Write = ID.Writes[Index]; in populateWrites()
355 WriteDescriptor &Write = ID.Writes[NumExplicitDefs + NumImplicitDefs]; in populateWrites()
387 WriteDescriptor &Write = ID.Writes[CurrentDef]; in populateWrites()
401 ID.Writes.resize(CurrentDef); in populateWrites()
665 if (D.Writes.empty()) in createInstruction()
670 APInt WriteMask(D.Writes.size(), 0); in createInstruction()
679 for (const WriteDescriptor &WD : D.Writes) { in createInstruction()
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| /freebsd-12.1/contrib/llvm/include/llvm/MCA/HardwareUnits/ |
| H A D | RegisterFile.h | 179 SmallVectorImpl<WriteRef> &Writes) const;
199 void addRegisterRead(ReadState &RS, SmallVectorImpl<WriteRef> &Writes) const;
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| /freebsd-12.1/contrib/llvm/include/llvm/IR/ |
| H A D | IntrinsicsARM.td | 97 // Writes to the GE bits.
104 // Writes to the GE bits.
107 // Writes to the GE bits.
118 // Writes to the GE bits.
138 // Writes to the GE bits.
141 // Writes to the GE bits.
152 // Writes to the GE bits.
155 // Writes to the GE bits.
158 // Writes to the GE bits.
161 // Writes to the GE bits.
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| /freebsd-12.1/contrib/llvm/include/llvm/MCA/ |
| H A D | Instruction.h | 251 void setDependentWrites(unsigned Writes) { in setDependentWrites() argument
252 DependentWrites = Writes; in setDependentWrites()
253 IsReady = !Writes; in setDependentWrites()
323 SmallVector<WriteDescriptor, 4> Writes; // Implicit writes are at the end. member
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| /freebsd-12.1/contrib/llvm/include/llvm/MC/ |
| H A D | MCInstrAnalysis.h | 89 APInt &Writes) const;
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| /freebsd-12.1/contrib/llvm/tools/lld/docs/ |
| H A D | AtomLLD.rst | 14 * Writes standard Executable Files
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| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstrBundle.h | 157 bool Writes; member
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| /freebsd-12.1/crypto/openssl/doc/man1/ |
| H A D | rand.pod | 50 Writes random data to the specified I<file> upon exit.
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| H A D | gendsa.pod | 64 Writes random data to the specified I<file> upon exit.
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| H A D | speed.pod | 72 Writes random data to the specified I<file> upon exit.
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| H A D | passwd.pod | 104 Writes random data to the specified I<file> upon exit.
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| H A D | dsaparam.pod | 89 Writes random data to the specified I<file> upon exit.
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| H A D | genrsa.pod | 77 Writes random data to the specified I<file> upon exit.
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| H A D | dhparam.pod | 97 Writes random data to the specified I<file> upon exit.
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| H A D | ecparam.pod | 131 Writes random data to the specified I<file> upon exit.
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| /freebsd-12.1/sys/dev/ath/ath_hal/ar9001/ |
| H A D | ar9160.ini | 19 /* Auto Generated PCI Register Writes. Created: 05/22/08 */
633 /* Auto generated PCI Register Writes for SOWL1.0 ADDAC Shift Chain */
669 /* Auto generated PCI Register Writes for SOWL1.1 ADDAC Shift Chain */
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/ |
| H A D | MachineInstrBundle.cpp | 307 RI.Writes = true; in analyzeVirtReg()
|