| /freebsd-12.1/contrib/llvm/lib/CodeGen/ |
| H A D | LiveInterval.cpp | 1139 WriteI = ReadI = LR->begin(); in add()
1149 if (ReadI != WriteI) in add()
1152 if (ReadI == WriteI) in add()
1156 *WriteI++ = *ReadI++; in add()
1186 if (WriteI != LR->begin() && coalescable(WriteI[-1], Seg)) { in add()
1187 WriteI[-1].end = std::max(WriteI[-1].end, Seg.end); in add()
1192 if (WriteI != ReadI) { in add()
1193 *WriteI++ = Seg; in add()
1198 if (WriteI == E) { in add()
1200 WriteI = ReadI = LR->end(); in add()
[all …]
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedThunderX.td | 52 def : WriteRes<WriteI, [THXT8XUnitALU]> { let Latency = 1; }
202 def : ReadAdvance<ReadI, 2, [WriteImm, WriteI,
206 def THXT8XReadShifted : SchedReadAdvance<1, [WriteImm, WriteI,
210 def THXT8XReadNotShifted : SchedReadAdvance<2, [WriteImm, WriteI,
226 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
230 def : ReadAdvance<ReadIMA, 2, [WriteImm, WriteI,
236 def : ReadAdvance<ReadID, 1, [WriteImm, WriteI,
265 def : InstRW<[WriteI], (instrs COPY)>;
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| H A D | AArch64SchedA53.td | 60 def : WriteRes<WriteI, [A53UnitALU]> { let Latency = 3; }
158 def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
162 def A53ReadShifted : SchedReadAdvance<1, [WriteImm,WriteI,
166 def A53ReadNotShifted : SchedReadAdvance<2, [WriteImm,WriteI,
182 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
186 def : ReadAdvance<ReadIMA, 2, [WriteImm,WriteI,
192 def : ReadAdvance<ReadID, 1, [WriteImm,WriteI,
203 def : InstRW<[WriteI], (instrs COPY)>;
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| H A D | AArch64SchedThunderX2T99.td | 417 def : WriteRes<WriteI, [THX2T99I012]> {
423 def : InstRW<[WriteI],
436 def : InstRW<[WriteI], (instrs COPY)>;
583 // NOTE: Handled by WriteI.
600 // NOTE: Handled by WriteLD, WriteI.
721 def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRBpost)>;
722 def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRDpost)>;
723 def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRHpost)>;
724 def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRQpost)>;
725 def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRSpost)>;
[all …]
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| H A D | AArch64SchedKryo.td | 66 def : WriteRes<WriteI, [KryoUnitXY]> { let Latency = 1; }
130 def : InstRW<[WriteI], (instrs COPY)>;
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| H A D | AArch64SchedA57.td | 74 def : SchedAlias<WriteI, A57Write_1cyc_1I>;
130 def : InstRW<[WriteI], (instrs COPY)>;
145 SchedVar<NoSchedPred, [WriteI]>]>;
583 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRBpost)>;
589 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRDpost)>;
596 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRHpost)>;
602 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRQpost)>;
612 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRSpost)>;
|
| H A D | AArch64Schedule.td | 25 def WriteI : SchedWrite; // ALU
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| H A D | AArch64SchedFalkor.td | 71 def : WriteRes<WriteI, []> { let Unsupported = 1; }
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| H A D | AArch64SchedCyclone.td | 127 SchedVar<NoSchedPred, [WriteI]>]>;
151 def : WriteRes<WriteI, [CyUnitI]>;
293 def : InstRW<[WriteI], (instrs ISB)>;
360 def CyWriteCopyToGPR : WriteSequence<[WriteLD, WriteI]>;
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| H A D | AArch64InstrFormats.td | 1605 Sched<[WriteI, ReadI]> {
1640 Sched<[WriteI, ReadI]> {
1665 Sched<[WriteI, ReadI, ReadI]> {
1680 Sched<[WriteI, ReadI, ReadI]> {
1927 Sched<[WriteI]> {
1991 Sched<[WriteI, ReadI]> {
2022 Sched<[WriteI, ReadI]> {
2048 Sched<[WriteI, ReadI, ReadI]>;
2464 Sched<[WriteI, ReadI]> {
2560 Sched<[WriteI, ReadI, ReadI]>;
[all …]
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| H A D | AArch64SchedExynosM1.td | 137 def : WriteRes<WriteI, [M1UnitALU]> { let Latency = 1; }
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| H A D | AArch64SchedExynosM3.td | 187 def : SchedAlias<WriteI, M3WriteA1>;
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| H A D | AArch64SchedExynosM4.td | 500 def : SchedAlias<WriteI, M4WriteA1>;
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| H A D | AArch64InstrInfo.td | 1645 Sched<[WriteI, WriteLD, WriteI, WriteBrReg]>;
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| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | LiveInterval.h | 857 LiveRange::iterator WriteI; variable
|