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Searched refs:VT2 (Results 1 – 22 of 22) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h114 bool isTruncateFree(EVT VT1, EVT VT2) const override;
125 bool isZExtFree(EVT VT1, EVT VT2) const override;
126 bool isZExtFree(SDValue Val, EVT VT2) const override;
H A DMSP430ISelLowering.cpp1382 bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree()
1383 if (!VT1.isInteger() || !VT2.isInteger()) in isTruncateFree()
1386 return (VT1.getSizeInBits() > VT2.getSizeInBits()); in isTruncateFree()
1394 bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { in isZExtFree()
1396 return 0 && VT1 == MVT::i8 && VT2 == MVT::i16; in isZExtFree()
1399 bool MSP430TargetLowering::isZExtFree(SDValue Val, EVT VT2) const { in isZExtFree()
1400 return isZExtFree(Val.getValueType(), VT2); in isZExtFree()
/freebsd-12.1/contrib/llvm/include/llvm/IR/
H A DLegacyPassNameParser.h91 const PassNameParser::OptionInfo *VT2) { in ValCompare() argument
92 return VT1->Name.compare(VT2->Name); in ValCompare()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h547 SDVTList getVTList(EVT VT1, EVT VT2);
548 SDVTList getVTList(EVT VT1, EVT VT2, EVT VT3);
549 SDVTList getVTList(EVT VT1, EVT VT2, EVT VT3, EVT VT4);
1177 SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2);
1179 EVT VT2, ArrayRef<SDValue> Ops);
1181 EVT VT2, EVT VT3, ArrayRef<SDValue> Ops);
1183 EVT VT2, SDValue Op1);
1185 EVT VT2, SDValue Op1, SDValue Op2);
1215 EVT VT2, SDValue Op1, SDValue Op2);
1219 EVT VT2, ArrayRef<SDValue> Ops);
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H A DTargetLowering.h1215 MVT VT2; in getNumRegisters() local
1217 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2); in getNumRegisters()
2334 virtual bool isZExtFree(SDValue Val, EVT VT2) const { in isZExtFree() argument
2335 return isZExtFree(Val.getValueType(), VT2); in isZExtFree()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h323 bool isTruncateFree(EVT VT1, EVT VT2) const override;
328 bool isZExtFree(EVT VT1, EVT VT2) const override;
329 bool isZExtFree(SDValue Val, EVT VT2) const override;
H A DAArch64ISelLowering.cpp8165 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree()
8166 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger()) in isTruncateFree()
8169 unsigned NumBits2 = VT2.getSizeInBits(); in isTruncateFree()
8209 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { in isZExtFree()
8210 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger()) in isZExtFree()
8213 unsigned NumBits2 = VT2.getSizeInBits(); in isZExtFree()
8217 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const { in isZExtFree()
8219 if (isZExtFree(VT1, VT2)) { in isZExtFree()
8228 VT2.isSimple() && !VT2.isVector() && VT2.isInteger() && in isZExtFree()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86ISelLowering.h961 bool isTruncateFree(EVT VT1, EVT VT2) const override;
974 bool isZExtFree(EVT VT1, EVT VT2) const override;
975 bool isZExtFree(SDValue Val, EVT VT2) const override;
989 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
H A DX86ISelLowering.cpp27527 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree()
27528 if (!VT1.isInteger() || !VT2.isInteger()) in isTruncateFree()
27531 unsigned NumBits2 = VT2.getSizeInBits(); in isTruncateFree()
27540 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { in isZExtFree()
27542 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget.is64Bit(); in isZExtFree()
27545 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const { in isZExtFree()
27547 if (isZExtFree(VT1, VT2)) in isZExtFree()
27554 !VT2.isSimple() || !VT2.isInteger()) in isZExtFree()
27602 return !(VT1 == MVT::i32 && VT2 == MVT::i16); in isNarrowingProfitable()
30824 MVT VT2 = V2.getSimpleValueType(); in combineX86ShuffleChain() local
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/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.h158 bool isZExtFree(SDValue Val, EVT VT2) const override;
160 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
H A DAMDGPUISelLowering.cpp831 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const { in isZExtFree()
832 return isZExtFree(Val.getValueType(), VT2); in isZExtFree()
/freebsd-12.1/contrib/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h56 bool isZExtFree(SDValue Val, EVT VT2) const override;
H A DRISCVISelLowering.cpp261 bool RISCVTargetLowering::isZExtFree(SDValue Val, EVT VT2) const { in isZExtFree()
272 return TargetLowering::isZExtFree(Val, VT2); in isZExtFree()
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp7247 ID.AddInteger(VT2.getRawBits()); in getVTList()
7254 Array[1] = VT2; in getVTList()
7265 ID.AddInteger(VT2.getRawBits()); in getVTList()
7273 Array[1] = VT2; in getVTList()
7285 ID.AddInteger(VT2.getRawBits()); in getVTList()
7294 Array[1] = VT2; in getVTList()
7506 SDVTList VTs = getVTList(VT1, VT2); in SelectNodeTo()
7512 SDVTList VTs = getVTList(VT1, VT2); in SelectNodeTo()
7526 SDVTList VTs = getVTList(VT1, VT2); in SelectNodeTo()
7741 SDVTList VTs = getVTList(VT1, VT2); in getMachineNode()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/XCore/
H A DXCoreISelLowering.h100 bool isZExtFree(SDValue Val, EVT VT2) const override;
H A DXCoreISelLowering.cpp179 bool XCoreTargetLowering::isZExtFree(SDValue Val, EVT VT2) const { in isZExtFree()
185 !VT2.isSimple() || !VT2.isInteger()) in isZExtFree()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h797 bool isTruncateFree(EVT VT1, EVT VT2) const override;
799 bool isZExtFree(SDValue Val, EVT VT2) const override;
H A DPPCISelLowering.cpp14133 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree()
14134 if (!VT1.isInteger() || !VT2.isInteger()) in isTruncateFree()
14137 unsigned NumBits2 = VT2.getSizeInBits(); in isTruncateFree()
14141 bool PPCTargetLowering::isZExtFree(SDValue Val, EVT VT2) const { in isZExtFree()
14158 return TargetLowering::isZExtFree(Val, VT2); in isZExtFree()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h125 bool isTruncateFree(EVT VT1, EVT VT2) const override;
H A DHexagonISelLowering.cpp1823 bool HexagonTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree()
1824 if (!VT1.isSimple() || !VT2.isSimple()) in isTruncateFree()
1826 return VT1.getSimpleVT() == MVT::i64 && VT2.getSimpleVT() == MVT::i32; in isTruncateFree()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMISelLowering.h335 bool isZExtFree(SDValue Val, EVT VT2) const override;
H A DARMISelLowering.cpp13031 bool ARMTargetLowering::isZExtFree(SDValue Val, EVT VT2) const { in isZExtFree()
13037 !VT2.isSimple() || !VT2.isInteger()) in isZExtFree()