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Searched refs:VT1 (Results 1 – 20 of 20) sorted by relevance

/freebsd-12.1/contrib/llvm/include/llvm/IR/
H A DLegacyPassNameParser.h90 static int ValCompare(const PassNameParser::OptionInfo *VT1, in ValCompare() argument
92 return VT1->Name.compare(VT2->Name); in ValCompare()
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DAMDGPURewriteOutArguments.cpp212 VectorType *VT1 = dyn_cast<VectorType>(Ty1); in isVec3ToVec4Shuffle() local
213 if (!VT0 || !VT1) in isVec3ToVec4Shuffle()
217 VT1->getNumElements() != 4) in isVec3ToVec4Shuffle()
221 DL->getTypeSizeInBits(VT1->getElementType()); in isVec3ToVec4Shuffle()
H A DAMDGPUISelLowering.h160 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h547 SDVTList getVTList(EVT VT1, EVT VT2);
548 SDVTList getVTList(EVT VT1, EVT VT2, EVT VT3);
549 SDVTList getVTList(EVT VT1, EVT VT2, EVT VT3, EVT VT4);
1177 SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2);
1178 SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1,
1180 SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1,
1182 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1,
1184 SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1,
1214 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
1216 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
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H A DTargetLowering.h1186 EVT VT1; in getRegisterType() local
1189 (void)getVectorTypeBreakdown(Context, VT, VT1, in getRegisterType()
1214 EVT VT1; in getNumRegisters() local
1217 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2); in getNumRegisters()
/freebsd-12.1/contrib/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h114 bool isTruncateFree(EVT VT1, EVT VT2) const override;
125 bool isZExtFree(EVT VT1, EVT VT2) const override;
H A DMSP430ISelLowering.cpp1382 bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree() argument
1383 if (!VT1.isInteger() || !VT2.isInteger()) in isTruncateFree()
1386 return (VT1.getSizeInBits() > VT2.getSizeInBits()); in isTruncateFree()
1394 bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { in isZExtFree() argument
1396 return 0 && VT1 == MVT::i8 && VT2 == MVT::i16; in isZExtFree()
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp7246 ID.AddInteger(VT1.getRawBits()); in getVTList()
7253 Array[0] = VT1; in getVTList()
7264 ID.AddInteger(VT1.getRawBits()); in getVTList()
7272 Array[0] = VT1; in getVTList()
7284 ID.AddInteger(VT1.getRawBits()); in getVTList()
7293 Array[0] = VT1; in getVTList()
7506 SDVTList VTs = getVTList(VT1, VT2); in SelectNodeTo()
7512 SDVTList VTs = getVTList(VT1, VT2); in SelectNodeTo()
7526 SDVTList VTs = getVTList(VT1, VT2); in SelectNodeTo()
7741 SDVTList VTs = getVTList(VT1, VT2); in getMachineNode()
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H A DLegalizeVectorTypes.cpp3523 EVT VT1 = getSetCCResultType(SETCC1.getOperand(0).getValueType()); in WidenVSELECTAndMask() local
3525 unsigned ScalarBits1 = VT1.getScalarSizeInBits(); in WidenVSELECTAndMask()
3532 EVT NarrowVT = ((ScalarBits0 < ScalarBits1) ? VT0 : VT1); in WidenVSELECTAndMask()
3533 EVT WideVT = ((NarrowVT == VT0) ? VT1 : VT0); in WidenVSELECTAndMask()
3546 SETCC1 = convertMask(SETCC1, VT1, MaskVT); in WidenVSELECTAndMask()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86ISelLowering.h961 bool isTruncateFree(EVT VT1, EVT VT2) const override;
974 bool isZExtFree(EVT VT1, EVT VT2) const override;
989 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
H A DX86ISelLowering.cpp27528 if (!VT1.isInteger() || !VT2.isInteger()) in isTruncateFree()
27530 unsigned NumBits1 = VT1.getSizeInBits(); in isTruncateFree()
27546 EVT VT1 = Val.getValueType(); in isZExtFree() local
27547 if (isZExtFree(VT1, VT2)) in isZExtFree()
27553 if (!VT1.isSimple() || !VT1.isInteger() || in isZExtFree()
27557 switch (VT1.getSimpleVT().SimpleTy) { in isZExtFree()
27602 return !(VT1 == MVT::i32 && VT2 == MVT::i16); in isNarrowingProfitable()
30823 MVT VT1 = V1.getSimpleValueType(); in combineX86ShuffleChain() local
31762 EVT VT1 = BC1.getValueType(); in combineTargetShuffle() local
31765 if (Opcode0 == Opcode1 && VT0 == VT1 && in combineTargetShuffle()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h323 bool isTruncateFree(EVT VT1, EVT VT2) const override;
328 bool isZExtFree(EVT VT1, EVT VT2) const override;
H A DAArch64ISelLowering.cpp8165 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree() argument
8166 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger()) in isTruncateFree()
8168 unsigned NumBits1 = VT1.getSizeInBits(); in isTruncateFree()
8209 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { in isZExtFree() argument
8210 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger()) in isZExtFree()
8212 unsigned NumBits1 = VT1.getSizeInBits(); in isZExtFree()
8218 EVT VT1 = Val.getValueType(); in isZExtFree() local
8219 if (isZExtFree(VT1, VT2)) { in isZExtFree()
8227 return (VT1.isSimple() && !VT1.isVector() && VT1.isInteger() && in isZExtFree()
8229 VT1.getSizeInBits() <= 32); in isZExtFree()
/freebsd-12.1/contrib/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp183 EVT VT1 = Val.getValueType(); in isZExtFree() local
184 if (!VT1.isSimple() || !VT1.isInteger() || in isZExtFree()
188 switch (VT1.getSimpleVT().SimpleTy) { in isZExtFree()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h125 bool isTruncateFree(EVT VT1, EVT VT2) const override;
H A DHexagonISelLowering.cpp1823 bool HexagonTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree() argument
1824 if (!VT1.isSimple() || !VT2.isSimple()) in isTruncateFree()
1826 return VT1.getSimpleVT() == MVT::i64 && VT2.getSimpleVT() == MVT::i32; in isTruncateFree()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp76 for (MVT VT1 : MVT::vector_valuetypes()) { in MipsSETargetLowering() local
77 setTruncStoreAction(VT0, VT1, Expand); in MipsSETargetLowering()
78 setLoadExtAction(ISD::SEXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
79 setLoadExtAction(ISD::ZEXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
80 setLoadExtAction(ISD::EXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h797 bool isTruncateFree(EVT VT1, EVT VT2) const override;
H A DPPCISelLowering.cpp14133 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree() argument
14134 if (!VT1.isInteger() || !VT2.isInteger()) in isTruncateFree()
14136 unsigned NumBits1 = VT1.getSizeInBits(); in isTruncateFree()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp13035 EVT VT1 = Val.getValueType(); in isZExtFree() local
13036 if (!VT1.isSimple() || !VT1.isInteger() || in isZExtFree()
13040 switch (VT1.getSimpleVT().SimpleTy) { in isZExtFree()