Home
last modified time | relevance | path

Searched refs:VGPR0 (Results 1 – 7 of 7) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallingConv.td37 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
68 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
110 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
127 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
H A DSIInsertSkips.cpp171 .addReg(AMDGPU::VGPR0, RegState::Undef) in skipIfDead()
172 .addReg(AMDGPU::VGPR0, RegState::Undef) in skipIfDead()
173 .addReg(AMDGPU::VGPR0, RegState::Undef) in skipIfDead()
174 .addReg(AMDGPU::VGPR0, RegState::Undef) in skipIfDead()
H A DSIInsertWaitcnts.cpp122 unsigned VGPR0; member
469 assert(Reg >= RegisterEncoding.VGPR0 && Reg <= RegisterEncoding.VGPRL); in getRegInterval()
470 Result.first = Reg - RegisterEncoding.VGPR0; in getRegInterval()
1358 RegisterEncoding.VGPR0 = TRI->getEncodingValue(AMDGPU::VGPR0); in runOnMachineFunction()
1360 RegisterEncoding.VGPR0 + HardwareLimits.NumVGPRsMax - 1; in runOnMachineFunction()
H A DSIMachineFunctionInfo.cpp314 return AMDGPU::VGPR0; in getWorkItemIDVGPR()
H A DSIRegisterInfo.cpp80 classifyPressureSet(i, AMDGPU::VGPR0, VGPRPressureSets); in SIRegisterInfo()
1177 REG_RANGE(AMDGPU::VGPR0, AMDGPU::VGPR255, VGPR32RegNames); in getRegAsmName()
H A DSOPInstructions.td658 // VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1
H A DSIISelLowering.cpp1489 unsigned Reg = AMDGPU::VGPR0; in allocateSpecialEntryInputVGPRs()
1902 CCInfo.AllocateReg(AMDGPU::VGPR0); in LowerFormalArguments()