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Searched refs:VGPR (Results 1 – 13 of 13) sorted by relevance

/freebsd-12.1/contrib/llvm/include/llvm/IR/
H A DIntrinsicsAMDGPU.td876 [llvm_any_ty, // vdata(VGPR)
888 [llvm_any_ty, // vdata(VGPR)
901 [LLVMMatchType<0>, // vdata(VGPR)
920 [LLVMMatchType<0>, // src(VGPR)
921 LLVMMatchType<0>, // cmp(VGPR)
931 [LLVMMatchType<0>, // vdata(VGPR)
951 [LLVMMatchType<0>, // src(VGPR)
952 LLVMMatchType<0>, // cmp(VGPR)
980 llvm_i32_ty, // vindex(VGPR)
1060 [llvm_i32_ty, // src(VGPR)
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.td142 // VGPR registers
144 def VGPR#Index : SIReg <"VGPR"#Index, Index> {
341 // VGPR 32-bit registers
349 // VGPR 64-bit registers
354 // VGPR 96-bit registers
360 // VGPR 128-bit registers
367 // VGPR 256-bit registers
378 // VGPR 512-bit registers
636 // VSrc_* Operands with an SGPR, VGPR or a 32-bit immediate
646 // VSrc_* Operands with an VGPR
[all …]
H A DSIMachineFunctionInfo.h195 unsigned VGPR = 0; member
199 SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) {} in SpilledReg()
202 bool hasReg() { return VGPR != 0;} in hasReg()
207 unsigned VGPR; member
213 SGPRSpillVGPRCSR(unsigned V, Optional<int> F) : VGPR(V), FI(F) {} in SGPRSpillVGPRCSR()
H A DAMDGPURegisterBanks.td14 def VGPRRegBank : RegisterBank<"VGPR",
H A DAMDGPUGenRegisterBankInfo.def50 {0, 1, VGPRRegBank}, // VGPR begin
H A DAMDGPUCallingConv.td89 (sequence "VGPR%u", 24, 255)
93 (sequence "VGPR%u", 32, 255)
H A DSIInstrInfo.td80 SDTCisVT<2, i32>, // vindex(VGPR)
81 SDTCisVT<3, i32>, // voffset(VGPR)
98 SDTCisVT<2, i32>, // vindex(VGPR)
99 SDTCisVT<3, i32>, // voffset(VGPR)
119 SDTCisVT<2, i32>, // vindex(VGPR)
120 SDTCisVT<3, i32>, // voffset(VGPR)
137 SDTCisVT<2, i32>, // vindex(VGPR)
138 SDTCisVT<3, i32>, // voffset(VGPR)
158 SDTCisVT<3, i32>, // vindex(VGPR)
184 SDTCisVT<4, i32>, // vindex(VGPR)
[all …]
H A DSIMachineFunctionInfo.cpp294 LaneVGPR = SpillVGPRs.back().VGPR; in allocateSGPRSpillToVGPR()
H A DSIRegisterInfo.cpp756 VGPRDefined = !SGPRSpillVGPRDefinedSet.insert(Spill.VGPR).second; in spillSGPR()
762 Spill.VGPR) in spillSGPR()
765 .addReg(Spill.VGPR, VGPRDefined ? 0 : RegState::Undef); in spillSGPR()
918 .addReg(Spill.VGPR) in restoreSGPR()
H A DSIPeepholeSDWA.cpp1180 unsigned VGPR = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in legalizeScalarOperands() local
1182 TII->get(AMDGPU::V_MOV_B32_e32), VGPR); in legalizeScalarOperands()
1188 Op.ChangeToRegister(VGPR, false); in legalizeScalarOperands()
H A DSIFrameLowering.cpp598 TII->storeRegToStackSlot(MBB, MBBI, Reg.VGPR, true, in emitPrologue()
618 TII->loadRegFromStackSlot(MBB, MBBI, Reg.VGPR, in emitEpilogue()
H A DVOP1Instructions.td249 // Restrict src0 to be VGPR
644 // Copy of v_mov_b32 with $vdst as a use operand for use with VGPR
H A DAMDGPU.td192 "Has VGPR mode register indexing"