Searched refs:UndefReg (Results 1 – 4 of 4) sorted by relevance
79 std::vector<unsigned> UndefReg; member in __anon298be07c0111::RegSeqInfo87 UndefReg.push_back(Chan); in RegSeqInfo()183 if (CurrentUndexIdx >= Untouched->UndefReg.size()) in tryMergeVector()186 ((*It).second, Untouched->UndefReg[CurrentUndexIdx++])); in tryMergeVector()213 std::vector<unsigned> UpdatedUndef = BaseRSI->UndefReg; in RebuildVector()252 RSI->UndefReg = UpdatedUndef; in RebuildVector()320 unsigned NeededUndefs = 4 - RSI.UndefReg.size(); in tryMergeUsingFreeSlot()335 PreviousRegSeqByUndefCount[RSI.UndefReg.size()].push_back(RSI.Instr); in trackRSI()
423 unsigned UndefReg = createLaneMaskReg(MF); in insertUndefLaneMask() local425 UndefReg); in insertUndefLaneMask()426 return UndefReg; in insertUndefLaneMask()
9272 SDValue UndefReg = DAG.getRegister(MRI.createVirtualRegister(RC), VT); in PostISelFolding() local9275 UndefReg, Src0, SDValue()); in PostISelFolding()9289 Src0 = UndefReg; in PostISelFolding()9290 Src1 = UndefReg; in PostISelFolding()
536 unsigned UndefReg = MRI->createVirtualRegister(&X86::GR64RegClass); in adjustCallSequence() local538 BuildMI(MBB, Context.Call, DL, TII->get(X86::IMPLICIT_DEF), UndefReg); in adjustCallSequence()540 .addReg(UndefReg) in adjustCallSequence()