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Searched refs:UZP1 (Results 1 – 6 of 6) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h104 UZP1, enumerator
H A DAArch64SchedKryoDetails.td2330 (instregex "((TRN1|TRN2|ZIP1|UZP1|UZP2)v2i64|ZIP2(v2i64|v4i32|v8i16|v16i8))")>;
2360 (instregex "(UZP1|UZP2)(v4i32|v8i16|v16i8)")>;
2366 (instregex "(UZP1|UZP2|ZIP1|ZIP2)(v2i32|v4i16|v8i8)")>;
H A DAArch64ISelLowering.cpp1133 case AArch64ISD::UZP1: return "AArch64ISD::UZP1"; in getTargetNodeName()
6488 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS, in GeneratePerfectShuffle()
6660 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2; in LowerVECTOR_SHUFFLE()
6673 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2; in LowerVECTOR_SHUFFLE()
7345 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), LHS, in LowerBUILD_VECTOR()
H A DAArch64SchedFalkorDetails.td921 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(TRN1|TRN2|ZIP1|UZP1|UZP2|ZIP2|XTN)(v2i32|v2i64|…
H A DAArch64SchedThunderX2T99.td1538 (instregex "^UZP1", "^UZP2", "^ZIP1", "^ZIP2")>;
H A DAArch64InstrInfo.td305 def AArch64uzp1 : SDNode<"AArch64ISD::UZP1", SDT_AArch64Zip>;
4310 defm UZP1 : SIMDZipVector<0b001, "uzp1", AArch64uzp1>;