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Searched refs:TSFlags (Results 1 – 25 of 77) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h320 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
328 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
344 return get(Opcode).TSFlags & SIInstrFlags::SOP1; in isSOP1()
352 return get(Opcode).TSFlags & SIInstrFlags::SOP2; in isSOP2()
446 return MI.getDesc().TSFlags & SIInstrFlags::DS; in isDS()
450 return get(Opcode).TSFlags & SIInstrFlags::DS; in isDS()
478 auto Flags = MI.getDesc().TSFlags; in isSegmentSpecificFLAT()
492 return get(Opcode).TSFlags & SIInstrFlags::EXP; in isEXP()
500 return get(Opcode).TSFlags & SIInstrFlags::WQM; in isWQM()
532 return get(Opcode).TSFlags & SIInstrFlags::DPP; in isDPP()
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H A DSIInstrFormats.td129 let TSFlags{0} = SALU;
130 let TSFlags{1} = VALU;
132 let TSFlags{2} = SOP1;
133 let TSFlags{3} = SOP2;
134 let TSFlags{4} = SOPC;
135 let TSFlags{5} = SOPK;
136 let TSFlags{6} = SOPP;
138 let TSFlags{7} = VOP1;
139 let TSFlags{8} = VOP2;
140 let TSFlags{9} = VOPC;
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H A DR600InstrFormats.td54 let TSFlags{4} = Trig;
55 let TSFlags{5} = Op3;
59 let TSFlags{6} = isVector;
62 let TSFlags{10} = Op1;
63 let TSFlags{11} = Op2;
64 let TSFlags{12} = VTXInst;
65 let TSFlags{13} = TEXInst;
66 let TSFlags{14} = ALUInst;
67 let TSFlags{15} = LDS_1A;
68 let TSFlags{16} = LDS_1A1D;
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H A DR600Defines.h62 #define IS_VTX(desc) ((desc).TSFlags & R600_InstFlag::VTX_INST)
63 #define IS_TEX(desc) ((desc).TSFlags & R600_InstFlag::TEX_INST)
H A DVOPInstructions.td156 let TSFlags = ps.TSFlags;
456 let TSFlags = ps.TSFlags;
485 let TSFlags = ps.TSFlags;
568 let TSFlags = ps.TSFlags;
H A DSIMemoryLegalizer.cpp533 assert(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic); in getLoadInfo()
547 assert(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic); in getStoreInfo()
561 assert(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic); in getAtomicFenceInfo()
594 assert(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic); in getAtomicCmpxchgOrRmwInfo()
1022 if (!(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic)) in runOnMachineFunction()
H A DR600OptimizeVectorRegisters.cpp159 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST) in canSwizzle()
273 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST) in SwizzleInput()
358 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST) { in runOnMachineFunction()
H A DR600InstrInfo.h319 return get(MI.getOpcode()).TSFlags & R600InstrFlags::REGISTER_STORE; in isRegisterStore()
323 return get(MI.getOpcode()).TSFlags & R600InstrFlags::REGISTER_LOAD; in isRegisterLoad()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonInstrFormats.td72 let TSFlags{6-0} = Type.Value;
76 let TSFlags{7} = isSolo;
79 let TSFlags{8} = isSoloAX;
82 let TSFlags{9} = isRestrictSlot1AOK;
86 let TSFlags{10} = isPredicated;
90 let TSFlags{12} = isPredicatedNew;
125 let TSFlags{36} = cofMax1;
127 let TSFlags{37} = cofRelax1;
129 let TSFlags{38} = cofRelax2;
157 let TSFlags{56} = isAccumulator;
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H A DHexagonInstrFormatsV5.td52 let TSFlags{6-0} = Type.Value;
56 let TSFlags{7} = isPredicated;
58 let TSFlags{8} = isPredicatedFalse;
60 let TSFlags{9} = isPredicatedNew;
64 let TSFlags{10} = isNewValue; // New-value consumer insn.
66 let TSFlags{11} = hasNewValue; // New-value producer insn.
68 let TSFlags{14-12} = opNewValue; // New-value produced operand.
72 let TSFlags{16} = isNVStore; // New-value store insn.
76 let TSFlags{17} = isExtendable; // Insn may be extended.
78 let TSFlags{18} = isExtended; // Insn must be extended.
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H A DHexagonInstrInfo.cpp1515 const uint64_t F = MI.getDesc().TSFlags; in isPredicated()
1962 const uint64_t F = MI.getDesc().TSFlags; in isAccumulator()
2134 const uint64_t F = MID.TSFlags; in isExtendable()
2169 const uint64_t F = get(Opcode).TSFlags; in isFloat()
2361 const uint64_t F = get(Opcode).TSFlags; in isNewValue()
2383 const uint64_t F = get(Opcode).TSFlags; in isNewValueStore()
2402 const uint64_t F = get(Opcode).TSFlags; in isPredicatedNew()
2414 const uint64_t F = get(Opcode).TSFlags; in isPredicatedTrue()
2422 const uint64_t F = get(Opcode).TSFlags; in isPredicated()
2427 const uint64_t F = get(Opcode).TSFlags; in isPredicateLate()
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/freebsd-12.1/contrib/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp198 if (X86II::isImmSigned(TSFlags)) { in getImmFixupKind()
679 switch (TSFlags & X86II::OpMapMask) { in EmitVEXOpcodePrefix()
740 switch (TSFlags & X86II::FormMask) { in EmitVEXOpcodePrefix()
1037 if (TSFlags & X86II::REX_W) in DetermineREXPrefix()
1058 switch (TSFlags & X86II::FormMask) { in DetermineREXPrefix()
1172 switch (TSFlags & X86II::OpMapMask) { in emitOpcodePrefix()
1198 uint64_t TSFlags = Desc.TSFlags; in encodeInstruction() local
1338 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), in encodeInstruction()
1345 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), in encodeInstruction()
1353 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), in encodeInstruction()
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H A DX86BaseInfo.h589 return TSFlags >> X86II::OpcodeShift; in getBaseOpcodeFor()
592 inline bool hasImm(uint64_t TSFlags) { in hasImm() argument
593 return (TSFlags & X86II::ImmMask) != 0; in hasImm()
599 switch (TSFlags & X86II::ImmMask) { in getSizeOfImm()
616 switch (TSFlags & X86II::ImmMask) { in isImmPCRel()
635 switch (TSFlags & X86II::ImmMask) { in isImmSigned()
700 bool HasVEX_4V = TSFlags & X86II::VEX_4V; in getMemoryOperandNo()
703 switch (TSFlags & X86II::FormMask) { in getMemoryOperandNo()
812 inline bool isKMasked(uint64_t TSFlags) { in isKMasked() argument
813 return (TSFlags & X86II::EVEX_K) != 0; in isKMasked()
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/freebsd-12.1/contrib/llvm/lib/Target/NVPTX/
H A DNVPTXInstrFormats.td50 let TSFlags{3-0} = VecInstType;
51 let TSFlags{4-4} = IsSimpleMove;
52 let TSFlags{5-5} = IsLoad;
53 let TSFlags{6-6} = IsStore;
54 let TSFlags{7} = IsTex;
55 let TSFlags{9-8} = IsSuld;
56 let TSFlags{10} = IsSust;
57 let TSFlags{11} = IsSurfTexQuery;
58 let TSFlags{12} = IsTexModeUnified;
H A DNVPTXReplaceImageHandles.cpp83 if (MCID.TSFlags & NVPTXII::IsTexFlag) { in processInstr()
89 if (!(MCID.TSFlags & NVPTXII::IsTexModeUnifiedFlag)) { in processInstr()
95 } else if (MCID.TSFlags & NVPTXII::IsSuldMask) { in processInstr()
97 1 << (((MCID.TSFlags & NVPTXII::IsSuldMask) >> NVPTXII::IsSuldShift) - 1); in processInstr()
105 } else if (MCID.TSFlags & NVPTXII::IsSustFlag) { in processInstr()
112 } else if (MCID.TSFlags & NVPTXII::IsSurfTexQueryFlag) { in processInstr()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.cpp213 uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getMemAccessSize()
220 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getAddrMode()
288 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtendableOp()
306 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentAlignment()
312 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentBits()
318 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in isExtentSigned()
351 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getNewValueOp()
376 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getNewValueOp2()
395 const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags; in getType()
465 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in hasNewValue()
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/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86InstrFMA3Info.cpp133 const X86InstrFMA3Group *llvm::getFMA3Group(unsigned Opcode, uint64_t TSFlags) { in getFMA3Group() argument
136 uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); in getFMA3Group()
137 bool IsFMA3 = ((TSFlags & X86II::EncodingMask) == X86II::VEX || in getFMA3Group()
138 (TSFlags & X86II::EncodingMask) == X86II::EVEX) && in getFMA3Group()
139 (TSFlags & X86II::OpMapMask) == X86II::T8 && in getFMA3Group()
140 (TSFlags & X86II::OpPrefixMask) == X86II::PD && in getFMA3Group()
150 if (TSFlags & X86II::EVEX_RC) in getFMA3Group()
152 else if (TSFlags & X86II::EVEX_B) in getFMA3Group()
H A DX86EvexToVex.cpp225 if ((Desc.TSFlags & X86II::EncodingMask) != X86II::EVEX) in CompressEvexToVexImpl()
231 if (Desc.TSFlags & (X86II::EVEX_K | X86II::EVEX_B)) in CompressEvexToVexImpl()
236 if (Desc.TSFlags & X86II::EVEX_L2) in CompressEvexToVexImpl()
255 (Desc.TSFlags & X86II::VEX_L) ? makeArrayRef(X86EvexToVex256CompressTable) in CompressEvexToVexImpl()
H A DX86InstrFormats.td214 // the TSFlags creation below.
343 let TSFlags{6-0} = FormBits;
348 let TSFlags{15-13} = OpMapBits;
355 let TSFlags{29-28} = OpEncBits;
356 let TSFlags{37-30} = Opcode;
359 let TSFlags{39} = hasVEX_4V;
360 let TSFlags{40} = hasVEX_L;
361 let TSFlags{41} = hasEVEX_K;
362 let TSFlags{42} = hasEVEX_Z;
364 let TSFlags{44} = hasEVEX_B;
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H A DX86InstrFMA3Info.h98 const X86InstrFMA3Group *getFMA3Group(unsigned Opcode, uint64_t TSFlags);
H A DX86OptimizeLEAs.cpp338 int MemOpNo = X86II::getMemoryOperandNo(Desc.TSFlags) + in chooseBestLEA()
440 int MemOpNo = X86II::getMemoryOperandNo(Desc.TSFlags); in isReplaceable()
505 int MemOpNo = X86II::getMemoryOperandNo(Desc.TSFlags); in removeRedundantAddrCalc()
638 X86II::getMemoryOperandNo(Desc.TSFlags) + in removeRedundantLEAs()
/freebsd-12.1/contrib/llvm/lib/Target/X86/InstPrinter/
H A DX86InstPrinterCommon.cpp129 uint64_t TSFlags = Desc.TSFlags; in printInstFlags() local
132 if ((TSFlags & X86II::LOCK) || (Flags & X86::IP_HAS_LOCK)) in printInstFlags()
135 if ((TSFlags & X86II::NOTRACK) || (Flags & X86::IP_HAS_NOTRACK)) in printInstFlags()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp23 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; in hasRAWHazard()
44 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) { in getHazardType()
54 (LastMCID.TSFlags & ARMII::DomainMask) == ARMII::DomainGeneral) { in getHazardType()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp289 uint64_t TSFlags = MCID.TSFlags; in GetInstrType() local
291 isFirst = TSFlags & PPCII::PPC970_First; in GetInstrType()
292 isSingle = TSFlags & PPCII::PPC970_Single; in GetInstrType()
293 isCracked = TSFlags & PPCII::PPC970_Cracked; in GetInstrType()
294 return (PPCII::PPC970_Unit)(TSFlags & PPCII::PPC970_Mask); in GetInstrType()
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DR600MCCodeEmitter.cpp149 ((Desc.TSFlags & R600_InstFlag::OP1) || in encodeInstruction()
150 Desc.TSFlags & R600_InstFlag::OP2)) { in encodeInstruction()
176 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) in getMachineOpValue()

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