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Searched refs:ShiftOpc (Results 1 – 14 of 14) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMAddressingModes.h28 enum ShiftOpc { enum
44 inline const char *getShiftOpcStr(ShiftOpc Op) { in getShiftOpcStr()
55 inline unsigned getShiftOpcEncoding(ShiftOpc Op) { in getShiftOpcEncoding()
111 inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { in getSORegOpc()
115 inline ShiftOpc getSORegShOp(unsigned Op) { return (ShiftOpc)(Op & 7); } in getSORegShOp()
398 inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO,
410 inline ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) { in getAM2ShiftOpc()
411 return (ShiftOpc)((AM2Opc >> 13) & 7); in getAM2ShiftOpc()
H A DARMMCCodeEmitter.cpp219 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const { in getShiftOp()
1087 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); in getLdStSORegOpValue()
1125 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm); in getAddrMode2OffsetOpValue()
1340 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); in getSORegRegOpValue()
1385 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); in getSORegImmOpValue()
1490 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); in getT2SORegOpValue()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp62 bool selectShift(unsigned ShiftOpc, MachineInstrBuilder &MIB) const;
714 bool ARMInstructionSelector::selectShift(unsigned ShiftOpc, in selectShift() argument
717 MIB.addImm(ShiftOpc); in selectShift()
927 return selectShift(ARM_AM::ShiftOpc::lsr, MIB); in select()
929 return selectShift(ARM_AM::ShiftOpc::asr, MIB); in select()
931 return selectShift(ARM_AM::ShiftOpc::lsl, MIB); in select()
H A DARMSelectionDAGInfo.h24 static inline ShiftOpc getShiftOpcForNode(unsigned Opcode) { in getShiftOpcForNode()
H A DARMFastISel.cpp187 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
2702 ARM_AM::ShiftOpc Shift = (ARM_AM::ShiftOpc) ITP->Shift; in ARMEmitIntExt()
2729 ARM_AM::ShiftOpc ShiftAM = isLsl ? ARM_AM::lsl : Shift; in ARMEmitIntExt()
2775 ARM_AM::ShiftOpc ShiftTy) { in SelectShift()
H A DARMISelDAGToDAG.cpp83 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
440 ARM_AM::ShiftOpc ShOpcVal, in isShifterOpProfitable()
532 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); in SelectImmShifterOperand()
556 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); in SelectRegShifterOperand()
678 ARM_AM::ShiftOpc ShOpcVal = in SelectLdStSOReg()
758 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); in SelectAddrMode2OffsetReg()
1273 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode()); in SelectT2AddrModeSoReg()
2332 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(ISD::SRL); in tryV6T2BitfieldExtractOp()
H A DARMBaseInstrInfo.cpp198 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); in convertToThreeAddress()
603 ARM_AM::ShiftOpc ShiftOpc = ARM_AM::getAM2ShiftOpc(OffImm); in isLdstScaledRegNotPlusLsl2() local
604 if (ShiftOpc == ARM_AM::no_shift) return false; // not scaled in isLdstScaledRegNotPlusLsl2()
605 bool SimpleScaled = (isAdd && ShiftOpc == ARM_AM::lsl && Amt == 2); in isLdstScaledRegNotPlusLsl2()
H A DARMISelLowering.cpp13399 ARM_AM::ShiftOpc ShOpcVal= in getARMIndexedAddressParts()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonSplitDouble.cpp804 unsigned ShiftOpc = Left ? S2_asl_i_r in splitShift() local
842 BuildMI(B, MI, DL, TII->get(ShiftOpc), (Left ? LoR : TmpR)) in splitShift()
859 BuildMI(B, MI, DL, TII->get(ShiftOpc), HiR) in splitShift()
888 BuildMI(B, MI, DL, TII->get(ShiftOpc), (Left ? HiR : LoR)) in splitShift()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp390 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
752 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
762 ARM_AM::ShiftOpc ShiftTy;
772 ARM_AM::ShiftOpc ShiftTy;
779 ARM_AM::ShiftOpc ShiftTy;
3123 unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType, in CreateMem()
3447 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) in tryParseShiftRegister()
4899 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift; in parsePostIdxReg()
5227 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift; in parseMemory()
8544 ARM_AM::ShiftOpc ShiftTy; in processInstruction()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.cpp53 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, in printRegImmShift()
379 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm()); in printSORegRegOperand()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1147 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; in DecodeSORegImmOperand()
1186 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; in DecodeSORegRegOperand()
1540 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; in DecodeAddrMode2IdxInstruction()
1585 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; in DecodeSORegMemOperand()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp2368 unsigned ShiftOpc = (VT == MVT::i32) ? AArch64::UBFMWri : AArch64::UBFMXri; in tryBitfieldInsertOpFromOr() local
2370 ShiftOpc, DL, VT, Src, CurDAG->getTargetConstant(LSB, DL, VT), in tryBitfieldInsertOpFromOr()
H A DAArch64ISelLowering.cpp7044 unsigned ShiftOpc = Shift.getOpcode(); in tryLowerToSLI() local
7045 if ((ShiftOpc != AArch64ISD::VSHL && ShiftOpc != AArch64ISD::VLSHR)) in tryLowerToSLI()
7047 bool IsShiftRight = ShiftOpc == AArch64ISD::VLSHR; in tryLowerToSLI()