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Searched refs:ShiftOp (Results 1 – 7 of 7) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.cpp728 unsigned ShiftOp = MI->getOperand(OpNum).getImm(); in printShiftImmOperand() local
729 bool isASR = (ShiftOp & (1 << 5)) != 0; in printShiftImmOperand()
730 unsigned Amt = ShiftOp & 0x1f; in printShiftImmOperand()
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp616 unsigned ShiftOp; in PromoteIntRes_ADDSUBSAT() local
620 ShiftOp = ISD::SRA; in PromoteIntRes_ADDSUBSAT()
624 ShiftOp = ISD::SRL; in PromoteIntRes_ADDSUBSAT()
646 return DAG.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount); in PromoteIntRes_ADDSUBSAT()
2781 SDValue ShiftOp = N->getOperand(1); in ExpandIntRes_Shift() local
2786 if (ShiftOp.getValueType() != ShiftTy) in ExpandIntRes_Shift()
2787 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy); in ExpandIntRes_Shift()
2789 SDValue Ops[] = { LHSL, LHSH, ShiftOp }; in ExpandIntRes_Shift()
H A DDAGCombiner.cpp1995 SDValue ShiftOp = IsAdd ? N->getOperand(0) : N->getOperand(1); in foldAddSubOfSignBit() local
1997 if (!C || ShiftOp.getOpcode() != ISD::SRL) in foldAddSubOfSignBit()
2001 SDValue Not = ShiftOp.getOperand(0); in foldAddSubOfSignBit()
2006 EVT VT = ShiftOp.getValueType(); in foldAddSubOfSignBit()
2007 SDValue ShAmt = ShiftOp.getOperand(1); in foldAddSubOfSignBit()
5819 auto ShiftOp = dyn_cast<ConstantSDNode>(Op->getOperand(1)); in calculateByteProvider() local
5820 if (!ShiftOp) in calculateByteProvider()
5823 uint64_t BitShift = ShiftOp->getZExtValue(); in calculateByteProvider()
H A DSelectionDAGBuilder.cpp2413 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT); in visitBitTestCase() local
2422 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT), in visitBitTestCase()
2428 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT), in visitBitTestCase()
2433 DAG.getConstant(1, dl, VT), ShiftOp); in visitBitTestCase()
/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp1779 unsigned ShiftOp = TrueOp->getSExtValue() == 1 ? ISD::SRL : ISD::SRA; in expandSelectBoolean() local
1780 Result = CurDAG->getNode(ShiftOp, DL, MVT::i32, Result, in expandSelectBoolean()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp3301 unsigned ShiftOp = Subtarget.isABI_N64() ? Mips::DSLL : Mips::SLL; in emitINSERT_DF_VIDX() local
3346 BuildMI(*BB, MI, DL, TII->get(ShiftOp), LaneTmp1) in emitINSERT_DF_VIDX()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp199 for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) { in X86TargetLowering()
200 setOperationAction(ShiftOp , MVT::i16 , Custom); in X86TargetLowering()
201 setOperationAction(ShiftOp , MVT::i32 , Custom); in X86TargetLowering()
203 setOperationAction(ShiftOp , MVT::i64 , Custom); in X86TargetLowering()
36883 SDValue ShiftOp = Shift.getOperand(0); in foldXorTruncShiftIntoCmp() local
36884 EVT ShiftOpTy = ShiftOp.getValueType(); in foldXorTruncShiftIntoCmp()
36888 SDValue Cond = DAG.getSetCC(DL, SetCCResultType, ShiftOp, in foldXorTruncShiftIntoCmp()